kernel/drivers/clk/rockchip/clk.h, branch linux-6.9.y

clk: rockchip: rk3588: fix CLK_NR_CLKS usage

2024-02-27T16:04:58Z

CLK_NR_CLKS is not part of the DT bindings and needs to be removed from it, just like it recently happened for other platforms. This takes care of it by introducing a new function identifying the maximum used clock ID at runtime. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240126182919.48402-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner

clk: rockchip: add clock controller for the RK3588

2022-11-15T10:37:41Z

Add full clock controller support RK3588. [rebase, integrate fixes from Wyon and Finley, add missing frequencies to PLL lookup table, update commit message, add GATE_LINK clocks which downstream handles in its own driver with one DT node per clock] Signed-off-by: Wyon Bi Signed-off-by: Finley Xiao Signed-off-by: Elaine Zhang Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-10-sebastian.reichel@collabora.com [dropped module stuff after talking to Sebastian] Signed-off-by: Heiko Stuebner

clk: rockchip: add lookup table support

2022-11-14T14:35:07Z

Add support for mapping reset IDs to register offsets to support gapless continous platform reset IDs. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-9-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner

clk: rockchip: simplify rockchip_clk_add_lookup

2022-11-14T14:35:07Z

rockchip_clk_add_lookup is only called from within the file, so it can be made static. The additional checks are removed with the following reasoning: 1. The data structure is initialized by rockchip_clk_init(), which is called by all rockchip platforms before the clocks are registered. Not doing so would result in an incomplete clock tree at the moment, which is a fatal error. In other parts of the kernel these kind of checks are usually omitted, so this was done here. The alternative is adding a pr_err to inform the kernel programmer adding a new platform about his incorrect code. Apart from that we are also not checking if the clock id is within the array boundings. 2. While not used so far by any rockchip platform, 0 is a valid clock identifier. To align rockchip closer to other ARM platforms we will start using it with rk3588. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-8-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner

clk: rockchip: allow additional mux options for cpu-clock frequency changes

2022-11-14T14:34:18Z

In order to improve the main frequency of CPU, the clock path of CPU is simplified as follows: |--\ | \ |--\ --apll--|\ | \ | \ | |--apll_core--| \ | \ --24M---|/ |mux1 |--[gate]--|mux2|---clk_core | / | / --gpll--|\ | / |------| / | |--gpll_core--| / | |--/ --24M---|/ |--/ | | -------apll_directly--------------| When the CPU requests high frequency, we want to use MUX2 select the "apll_directly". At low frequencies use MUX1 to select “apll_core" and then MUX2 to select "apll_core_gate". However, in this way, the CPU frequency conversion needs to be in the following order: 1. MUX2 select to "apll_core_gate", MUX1 select "gpll_core" 2. Apll sets slow_mode, sets APLL parameters, locks APLL, and then APLL sets normal_mode 3. MUX1 select "apll_core", MUX2 select "apll_directly" So add pre_mux and post_mux options to cover this special requirements. Signed-off-by: Elaine Zhang [rebase] Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-7-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner

clk: rockchip: add pll type for RK3588

2022-11-14T14:33:46Z

Add RK3588 PLL support fully relying on lookup tables like the other upstream supported rockchip platforms. Signed-off-by: Elaine Zhang [rebase and modify code to avoid PLL parameter calculation] Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-6-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner

clk: rockchip: add register offset of the cores select parent

2022-11-14T14:33:45Z

The cores select parent register is special on RK3588. Signed-off-by: Elaine Zhang Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-5-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner

clk: rockchip: Add clock controller support for RV1126 SoC

2022-09-23T09:15:30Z

Clock & Reset Unit (CRU) in RV1126 support clocks for CRU and CRU_PMU blocks. This patch is trying to add minimal Clock-Architecture Diagram's inferred from [1] authored by Finley Xiao. [1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/clk/rockchip/clk-rv1126.c Cc: linux-clk@vger.kernel.org Cc: Michael Turquette Cc: Stephen Boyd Signed-off-by: Finley Xiao Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20220915163947.1922183-5-jagan@edgeble.ai Signed-off-by: Heiko Stuebner

clk: rockchip: Add MUXTBL variant

2022-09-13T10:09:14Z

Add a clock branch consisting of a mux with non-standard select values. The parent in Mux table is sorted by priority. Use clk_register_mux_table() to register such a mux-clock. Cc: linux-clk@vger.kernel.org Cc: Michael Turquette Cc: Stephen Boyd Signed-off-by: Elaine Zhang Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20220907160207.3845791-3-jagan@edgeble.ai Signed-off-by: Heiko Stuebner

clk: rockchip: Optimize PLL table memory usage

2021-05-11T10:22:29Z

Before the change: The sizeof rk3568_pll_rates = 2544 Use union: The sizeof rk3568_pll_rates = 1696 In future Soc, more PLL types will be added, and the rockchip_pll_rate_table will add more members, and the space savings will be even more pronounced by using union. Signed-off-by: Elaine Zhang Link: https://lore.kernel.org/r/20210511090726.15146-1-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner