kernel/drivers/clk/rockchip/clk-cpu.c, branch linux-6.9.y

clk: rockchip: allow additional mux options for cpu-clock frequency changes

2022-11-14T14:34:18Z

In order to improve the main frequency of CPU, the clock path of CPU is simplified as follows: |--\ | \ |--\ --apll--|\ | \ | \ | |--apll_core--| \ | \ --24M---|/ |mux1 |--[gate]--|mux2|---clk_core | / | / --gpll--|\ | / |------| / | |--gpll_core--| / | |--/ --24M---|/ |--/ | | -------apll_directly--------------| When the CPU requests high frequency, we want to use MUX2 select the "apll_directly". At low frequencies use MUX1 to select “apll_core" and then MUX2 to select "apll_core_gate". However, in this way, the CPU frequency conversion needs to be in the following order: 1. MUX2 select to "apll_core_gate", MUX1 select "gpll_core" 2. Apll sets slow_mode, sets APLL parameters, locks APLL, and then APLL sets normal_mode 3. MUX1 select "apll_core", MUX2 select "apll_directly" So add pre_mux and post_mux options to cover this special requirements. Signed-off-by: Elaine Zhang [rebase] Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-7-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner

clk: rockchip: add register offset of the cores select parent

2022-11-14T14:33:45Z

The cores select parent register is special on RK3588. Signed-off-by: Elaine Zhang Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-5-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner

clk: rockchip: support more core div setting

2021-03-21T10:10:58Z

Use arrays to support more core independent div settings. A55 supports each core to work at different frequencies, and each core has an independent divider control. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20210315085608.16010-4-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner

clk: rockchip: Remove unused/undocumented struct members from clk-cpu

2021-01-25T23:24:05Z

Fixes the following W=1 kernel build warning(s): drivers/clk/rockchip/clk-cpu.c:65: warning: Function parameter or member 'cpu_mux' not described in 'rockchip_cpuclk' drivers/clk/rockchip/clk-cpu.c:65: warning: Function parameter or member 'cpu_mux_ops' not described in 'rockchip_cpuclk' Cc: Michael Turquette Cc: Stephen Boyd Cc: Heiko Stuebner Cc: Thomas Abraham Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20210120093040.1719407-3-lee.jones@linaro.org Signed-off-by: Heiko Stuebner

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

2019-06-19T15:09:55Z

Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Enrico Weigelt Reviewed-by: Kate Stewart Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman

clk: rockchip: Remove superfluous error message in rockchip_clk_register_cpuclk()

2017-09-28T13:22:50Z

Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring Signed-off-by: Heiko Stuebner

clk: rockchip: validity should be checked prior to cpu clock rate change

2016-11-14T11:20:53Z

If validity is not checked prior to clock rate change, clk_set_rate( cpu_clk, unsupported_rate) will return success, but the real clock rate change operation is prohibited in post clock change event. Alough post clock change event will report error due to unsupported clock rate is set, but this error message is ignored by clock framework. Signed-off-by: Elaine Zhang Tested-by: Rocky Hao Signed-off-by: Heiko Stuebner

clk: rockchip: fix cpuclk registration error handling

2016-05-30T07:40:23Z

It maybe due to a copy-paste error the error handing should be cclk not clk when checking if the cpuclk registration succeeded. Reported-by: Lin Huang Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner

clk: rockchip: allow varying mux parameters for cpuclk pll-sources

2016-03-27T11:03:33Z

Thers are only two parent PLLs that APLL and GPLL for core on the previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed GPLL as alternate parent when core is switching freq. Since RK3399 big.LITTLE architecture, we need to select and adapt more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources. Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner

clk: rockchip: fix coding style for clk-cpu.c

2016-02-15T22:38:35Z

Fix the issue reported by checkpatch: ERROR: space prohibited before that ',' (ctx:WxW) + writel(clksel->val , cpuclk->reg_base + clksel->reg); Signed-off-by: Shawn Lin Signed-off-by: Heiko Stuebner