kernel/drivers/clk/qcom/lcc-msm8960.c, branch linux-6.9.y

Merge branch 'clk-qcom' into clk-next

2023-08-30T21:39:58Z

* clk-qcom: (87 commits) clk: qcom: Fix SM_GPUCC_8450 dependencies clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC clk: qcom: smd-rpm: Add a way to define bus clocks with rate and flags clk: qcom: gcc-ipq5018: change some variable static clk: qcom: gcc-ipq4019: add missing networking resets dt-bindings: clock: qcom: ipq4019: add missing networking resets clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRC clk: qcom: gcc-qdu1000: Update the RCGs ops clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops clk: qcom: gcc-qdu1000: Add support for GDSCs clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock clk: qcom: gcc-qdu1000: Fix clkref clocks handling clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGs clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock clk: qcom: ipq5332: drop the mem noc clocks clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks ...

clk: qcom: lcc-msm8960: change pxo_parent_data to static

2023-08-03T15:01:21Z

The pxo_parent_data inroduced in commit bac4675a4d1b ("clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960") is only used in lcc-msm8960.c now, change it to static. Signed-off-by: Yang Yingliang Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230803082125.521849-1-yangyingliang@huawei.com Signed-off-by: Bjorn Andersson

clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960

2023-07-31T21:25:16Z

The two LCC drivers, msm8960 and mdm9615 are almost the same. The only difference is the platform clock: msm8960/apq8064 use pxo, while mdm9615 uses cxo. Drop the lcc-mdm9615 in favour of using lcc-msm8960 instead. Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230512211727.3445575-6-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson

clk: Explicitly include correct DT includes

2023-07-19T20:13:16Z

The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Acked-by: Dinh Nguyen Acked-by: Krzysztof Kozlowski # samsung Acked-by: Heiko Stuebner #rockchip Acked-by: Chanwoo Choi Acked-by: Geert Uytterhoeven Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Luca Ceresoli # versaclock5 Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230718143156.1066339-1-robh@kernel.org Acked-by: Abel Vesa #imx Signed-off-by: Stephen Boyd

clk: qcom: lcc-msm8960: use parent_hws/_data instead of parent_names

2022-09-14T02:58:34Z

Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by: Dmitry Baryshkov Tested-by: David Heidelberg # tested on Nexus 7 (2013) Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220623120418.250589-7-dmitry.baryshkov@linaro.org

clk: qcom: lcc-msm8960: use macros to implement mi2s clocks

2022-09-14T02:58:34Z

Split and extend existing CLK_AIF_OSR_DIV macro to implement mi2s clocks. This simplifies the driver and removes extra code duplication. The clock mi2s_div_clk used .enable_reg/.enable_bit, however these fields are not used with by the clk_regmap_div_ops, thus they are silently dropped. Clock enablement is handled in the mi2s_bit_div_clk clock. Signed-off-by: Dmitry Baryshkov Tested-by: David Heidelberg # tested on Nexus 7 (2013) Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220623120418.250589-6-dmitry.baryshkov@linaro.org

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282

2019-06-05T15:36:37Z

Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Alexios Zavras Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman

Revert "clk: qcom: Specify LE device endianness"

2016-02-12T22:24:24Z

This reverts commit 329cabcecf94d8d7821e729dda284ba9dec44c87. The commit that caused us to specify LE device endianness here, 29bb45f25ff3 (regmap-mmio: Use native endianness for read/write, 2015-10-29), has been reverted in mainline so now when we specify LE it actively breaks big endian kernels because the byte swapping in regmap-mmio is incorrect. Let's revert this change because it will 1) fix the big endian kernels and 2) be redundant to specify LE because that will become the default soon. Cc: Kevin Hilman Tested-by: Kevin Hilman Cc: Mark Brown Signed-off-by: Stephen Boyd

clk: qcom: Specify LE device endianness

2015-11-20T21:14:43Z

All these clock controllers are little endian devices, but so far we've been relying on the regmap mmio bus handling this for us without explicitly stating that fact. After commit 4a98da2164cf (regmap-mmio: Use native endianness for read/write, 2015-10-29), the regmap mmio bus will read/write with the __raw_*() IO accessors, instead of using the readl/writel() APIs that do proper byte swapping for little endian devices. So if we're running on a big endian processor and haven't specified the endianness explicitly in the regmap config or in DT, we're going to switch from doing little endian byte swapping to big endian accesses without byte swapping, leading to some confusing results. On my apq8074 dragonboard, this causes the device to fail to boot as we access the clock controller with big endian IO accesses even though the device is little endian. Specify the endianness explicitly so that the regmap core properly byte swaps the accesses for us. Reported-by: Kevin Hilman Tested-by: Tyler Baker Tested-by: Kevin Hilman Cc: Simon Arlott Cc: Mark Brown Signed-off-by: Stephen Boyd

clk: qcom: Drop calls to qcom_cc_remove()

2015-10-09T06:53:01Z

Now that qcom_cc_remove() is a nop, drop calls to qcom_cc_remove() and any empty driver remove functions. Cc: Rajendra Nayak Signed-off-by: Stephen Boyd