kernel/drivers/clk/qcom/clk-regmap-divider.c, branch linux-6.9.y

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282

2019-06-05T15:36:37Z

Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Alexios Zavras Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman

clk: qcom: use divider_ro_round_rate helper

2018-03-12T22:10:27Z

There is now an helper function to round the rate when the divider is read-only. Let's use it Signed-off-by: Jerome Brunet Signed-off-by: Michael Turquette Signed-off-by: Stephen Boyd

Merge branch 'clk-divider-container' into clk-next

2018-01-27T00:43:14Z

* clk-divider-container: clk: divider: fix incorrect usage of container_of Plus fixup sprd/div.c to pass the width too.

clk: divider: fix incorrect usage of container_of

2017-12-28T23:16:04Z

divider_recalc_rate() is an helper function used by clock divider of different types, so the structure containing the 'hw' pointer is not always a 'struct clk_divider' At the following line: > div = _get_div(table, val, flags, divider->width); in several cases, the value of 'divider->width' is garbage as the actual structure behind this memory is not a 'struct clk_divider' Fortunately, this width value is used by _get_val() only when CLK_DIVIDER_MAX_AT_ZERO flag is set. This has never been the case so far when the structure is not a 'struct clk_divider'. This is probably why we did not notice this bug before Fixes: afe76c8fd030 ("clk: allow a clk divider with max divisor when zero") Signed-off-by: Jerome Brunet Acked-by: Alexandre Belloni Acked-by: Sylvain Lemieux Signed-off-by: Stephen Boyd

clk: qcom: add read-only divider operations

2017-12-22T00:03:19Z

Some of the divider settings are preconfigured and should not be changed by the clock framework during frequency change. This patch adds the read-only divider operation for QCOM dividers which is equivalent to generic divider operations in 'commit 79c6ab509558 ("clk: divider: add CLK_DIVIDER_READ_ONLY flag")'. Signed-off-by: Abhishek Sahu Signed-off-by: Stephen Boyd

clk: qcom: Add support for regmap divider clocks

2015-01-27T19:49:00Z

Add support for dividers that use regmap instead of readl/writel. Signed-off-by: Josh Cartwright Signed-off-by: Rajendra Nayak [sboyd@codeaurora.org: Switch to using generic divider code, drop enable/disable, reword commit text] Signed-off-by: Stephen Boyd Tested-by: Kenneth Westfield Signed-off-by: Michael Turquette