<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/clk/qcom/clk-hfpll.c, branch linux-6.9.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.9.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.9.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2023-09-13T19:07:58Z</updated>
<entry>
<title>clk: qcom: clk-hfpll: Configure l_val in init when required</title>
<updated>2023-09-13T19:07:58Z</updated>
<author>
<name>Adam Skladowski</name>
<email>a39.skl@gmail.com</email>
</author>
<published>2023-08-12T11:24:45Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=500a4609eef46d49a260173b66cabb20bd5159ad'/>
<id>urn:sha1:500a4609eef46d49a260173b66cabb20bd5159ad</id>
<content type='text'>
Add support for pre-configuring default frequency multiplier,
this appears to be required on some platforms like MSM8976.
Without configuring L_VAL device reboots when trying to bring PLL up.

Signed-off-by: Adam Skladowski &lt;a39.skl@gmail.com&gt;
Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@linaro.org&gt;
Link: https://lore.kernel.org/r/20230812112534.8610-3-a39.skl@gmail.com
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: clk-hfpll: switch to .determine_rate</title>
<updated>2023-03-13T23:38:24Z</updated>
<author>
<name>Luca Weiss</name>
<email>luca@z3ntu.xyz</email>
</author>
<published>2023-02-12T14:11:09Z</published>
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<id>urn:sha1:04648b8fad219599ccc9b103188a38e72d339a3d</id>
<content type='text'>
.determine_rate is meant to replace .round_rate. The former comes with a
benefit which is especially relevant on 32-bit systems: since
.determine_rate uses an "unsigned long" (compared to a "signed long"
which is used by .round_rate) the maximum value on 32-bit systems
increases from 2^31 (or approx. 2.14GHz) to 2^32 (or approx. 4.29GHz).

Signed-off-by: Luca Weiss &lt;luca@z3ntu.xyz&gt;
Tested-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
Link: https://lore.kernel.org/r/20230212-clk-qcom-determine_rate-v1-2-b4e447d4926e@z3ntu.xyz
</content>
</entry>
<entry>
<title>clk: qcom: clk-hfpll: use poll_timeout macro</title>
<updated>2022-06-27T20:41:37Z</updated>
<author>
<name>Ansuel Smith</name>
<email>ansuelsmth@gmail.com</email>
</author>
<published>2022-04-30T05:44:56Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=fcfbfe373d41b4728ffec075f8f91b6572a88c27'/>
<id>urn:sha1:fcfbfe373d41b4728ffec075f8f91b6572a88c27</id>
<content type='text'>
Use regmap_read_poll_timeout macro instead of do-while structure to tidy
things up. Also set a timeout to prevent any sort of system stall.

Signed-off-by: Ansuel Smith &lt;ansuelsmth@gmail.com&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@linaro.org&gt;
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/20220430054458.31321-2-ansuelsmth@gmail.com
</content>
</entry>
<entry>
<title>clk: let init callback return an error code</title>
<updated>2019-12-24T02:53:13Z</updated>
<author>
<name>Jerome Brunet</name>
<email>jbrunet@baylibre.com</email>
</author>
<published>2019-09-24T12:39:53Z</published>
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<id>urn:sha1:89d079dc17e8a32397de827cc85c1f4911b90424</id>
<content type='text'>
If the init callback is allowed to request resources, it needs a return
value to report the outcome of such a request.

Signed-off-by: Jerome Brunet &lt;jbrunet@baylibre.com&gt;
Link: https://lkml.kernel.org/r/20190924123954.31561-3-jbrunet@baylibre.com
Reviewed-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Acked-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Add support for High-Frequency PLLs (HFPLLs)</title>
<updated>2018-10-17T20:14:37Z</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@codeaurora.org</email>
</author>
<published>2018-08-14T12:12:21Z</published>
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<id>urn:sha1:b3f2f10693aadeacf83ab5be03810941a4b77612</id>
<content type='text'>
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.

Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Sricharan R &lt;sricharan@codeaurora.org&gt;
Tested-by: Craig Tatlor &lt;ctatlor97@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
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