kernel/drivers/clk/qcom/a53-pll.c, branch linux-6.5.y

clk: qcom: a53-pll: convert to use parent_data rather than parent_names

2022-09-13T21:49:15Z

Change a53-pll driver to use clk_parent_data rather than always looking up the xo clock in the system clock list. Note, this change also switches the a53-pll from the global `xo' clock to the `xo_board', the clock that is specified as the `xo' clock in the DT file. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220909103137.3727830-1-dmitry.baryshkov@linaro.org

clk: qcom: a53-pll: Make use of the helper function devm_platform_ioremap_resource()

2021-09-14T21:39:14Z

Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing Link: https://lore.kernel.org/r/20210907084843.3999-1-caihuoqing@baidu.com Signed-off-by: Stephen Boyd

clk: qcom: a53-pll: Add MSM8939 a53pll support

2021-08-06T01:52:11Z

MSM8939 has 3 a53pll clocks with different frequency table for Cluster0, Cluster1 and CCI. It adds function qcom_a53pll_get_freq_tbl() to create pll_freq_tbl from OPP, so that those a53pll frequencies can be defined in DT with operating-points-v2 bindings rather than being coded in the driver. In this case, one compatible rather than three would be needed for these 3 a53pll clocks. Signed-off-by: Shawn Guo Link: https://lore.kernel.org/r/20210704024032.11559-5-shawn.guo@linaro.org Signed-off-by: Stephen Boyd

clk: qcom: a53pll/mux: Use unique clock name

2021-08-06T01:52:11Z

Different from MSM8916 which has only one a53pll/mux clock, MSM8939 gets three for Cluster0 (little cores), Cluster1 (big cores) and CCI (Cache Coherent Interconnect). That said, a53pll/mux clock needs to be named uniquely. Append @unit-address of device node to the clock name, so that a53pll/mux will be named like below on MSM8939. a53pll@b016000 a53pll@b116000 a53pll@b1d0000 a53mux@b1d1000 a53mux@b011000 a53mux@b111000 Signed-off-by: Shawn Guo Link: https://lore.kernel.org/r/20210704024032.11559-3-shawn.guo@linaro.org Signed-off-by: Stephen Boyd

clk: qcom: apcs-msm8916: Flag a53mux instead of a53pll as critical

2021-08-06T01:52:11Z

The clock source for MSM8916 cpu cores is like below. |\ a53pll --------| \ a53mux +------+ | |------------| cpus | gpll0_vote --------| / +------+ |/ So a53mux rather than a53pll is actually the parent clock of cpu cores. It makes more sense to flag a53mux as critical instead, so that when either a53pll or gpll0_vote is used by cpu cores, the clock will be kept enabled while the other can be disabled. Signed-off-by: Shawn Guo Link: https://lore.kernel.org/r/20210704024032.11559-2-shawn.guo@linaro.org Signed-off-by: Stephen Boyd

clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLE

2021-04-09T18:20:53Z

CONFIG_QCOM_A53PLL is tristate option and therefore this driver can be compiled as a module. This patch adds missing MODULE_DEVICE_TABLE definition which generates correct modalias for automatic loading of this driver when it is built as an external module. Fixes: 0c6ab1b8f894 ("clk: qcom: Add A53 PLL support") Signed-off-by: Chen Hui Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20210409082352.233810-3-clare.chenhui@huawei.com Signed-off-by: Stephen Boyd

clk: qcom: Add A53 PLL support

2018-01-02T18:00:24Z

The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources are connected to a mux and half-integer divider, which is feeding the CPU cores. This patch adds support for the primary CPU PLL which generates the higher range of frequencies above 1GHz. Signed-off-by: Georgi Djakov Acked-by: Bjorn Andersson Tested-by: Amit Kucheria [sboyd@codeaurora.org: Move to devm provider registration, NUL terminate frequency table, made tristate/modular] Signed-off-by: Stephen Boyd