kernel/drivers/clk/meson, branch linux-5.1.y

clk: meson: vid-pll-div: remove warning and return 0 on invalid config

2019-03-29T08:41:30Z

The vid_pll_div is a programmable fractional divider, but vendor gives a limited of known configuration value and it's corresponding fraction. Thus when at reset value (0) or unknown value, we cannot determine the result rate. The initial behaviour was to print a warning, but the warning triggers at each boot and when the clock tree is refreshed. This patch moves the print to debug and returns 0 instead of the parent rate. Fixes: 72dbb8c94d0d ("clk: meson: Add vid_pll divider driver") Signed-off-by: Neil Armstrong Reviewed-by: Jerome Brunet Link: https://lkml.kernel.org/r/20190327151348.27402-1-narmstrong@baylibre.com

clk: meson: pll: fix rounding and setting a rate that matches precisely

2019-03-25T12:18:09Z

Make meson_clk_pll_is_better() consider a rate that precisely matches the requested rate to be better than any previous rate (which was smaller than the current). Prior to commit 8eed1db1adec6a ("clk: meson: pll: update driver for the g12a") meson_clk_get_pll_settings() returned early (before calling meson_clk_pll_is_better()) if the rate from the current iteration matches the requested rate precisely. After this commit meson_clk_pll_is_better() is called unconditionally. This requires meson_clk_pll_is_better() to work with the case where "now == rate". This fixes a hang during boot on Meson8b / Odroid-C1 for me. Fixes: 8eed1db1adec6a ("clk: meson: pll: update driver for the g12a") Signed-off-by: Martin Blumenstingl Reviewed-by: Jerome Brunet Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190324164327.22590-2-martin.blumenstingl@googlemail.com

clk: meson-g12a: fix VPU clock parents

2019-03-19T16:38:41Z

First two VPU clock parents are wrong, fix it here. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Neil Armstrong Acked-by: Jerome Brunet Link: https://lkml.kernel.org/r/20190313135503.3198-1-narmstrong@baylibre.com

clk: meson: g12a: fix VPU clock muxes mask

2019-03-19T16:38:00Z

There are 8 parents, use 0x7 Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Maxime Jourdan Acked-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190319082611.6215-1-mjourdan@baylibre.com

clk: meson-gxbb: round the vdec dividers to closest

2019-03-19T16:36:37Z

We want the video decoder clocks to always round to closest. While the muxes are already using CLK_MUX_ROUND_CLOSEST, the corresponding CLK_DIVIDER_ROUND_CLOSEST was forgotten for the dividers. Fix this by adding the flag to the two vdec dividers. Fixes: a565242eb9fc ("clk: meson: gxbb: add the video decoder clocks") Signed-off-by: Maxime Jourdan Acked-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190319102537.2043-1-mjourdan@baylibre.com

clk: meson: meson8b: fix the naming of the APB clocks

2019-02-13T08:51:09Z

Fix a typo in the APB clock names by renaming them from "abp" to "apb". No functional changes. Fixes: a7d19b05ce817d ("clk: meson: meson8b: add the CPU clock post divider clocks") Signed-off-by: Martin Blumenstingl Signed-off-by: Neil Armstrong Acked-by: Jerome Brunet Link: https://lkml.kernel.org/r/20190210222603.6404-2-martin.blumenstingl@googlemail.com

clk: meson: Add G12A AO Clock + Reset Controller

2019-02-13T08:49:32Z

Add the Amlogic G12A AO Clock and Reset controller driver handling generation of Always-On clocks : - AO Clocks and Reset for Always-On modules - 32K Generation for USB and CEC - SAR ADC controller clock Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Acked-by: Jerome Brunet Link: https://lkml.kernel.org/r/20190212162859.20743-3-narmstrong@baylibre.com

clk: meson: factorise meson64 peripheral clock controller drivers

2019-02-04T08:52:11Z

The function used to probe the peripheral clock controller of the arm64 amlogic SoCs is mostly the same. We now have 3 of those controllers so it is time to factorize things a bit. Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190201145345.6795-5-jbrunet@baylibre.com

clk: meson: g12a: add peripheral clock controller

2019-02-04T08:52:11Z

Add the peripheral clock controller found in the g12a SoC family Signed-off-by: Jian Hu Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190201145345.6795-4-jbrunet@baylibre.com

clk: meson: pll: update driver for the g12a

2019-02-04T08:51:37Z

The g12a use fractional parameter of 17 useful bits. At the moment, this parameter in encoded using u16 value. Use this opportunity to switch all the pll to parameter to unsigned int. This should save us some annoying trouble shooting when and m and n field eventually grow as well. This patch also introduce pll multiplier range. On the g12a, the hifi and gp0 plls are able to lock as long as the following condition is met: 55 <= m/n <= 255. The param table describing this would be huge which is a waste of memory. Using ranges, we can save memory. Ranges also help find the best pll parameter significantly faster since we don't have to try all the possible settings. Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong [jbrunet: fixed fix pll settings calculation with arm32] Link: https://lkml.kernel.org/r/20190201145345.6795-2-jbrunet@baylibre.com