kernel/drivers/clk/meson/clk-phase.c, branch linux-6.9.y

clk: meson: add sclk-ws driver

2020-08-17T13:58:02Z

This is yet another simple but odd driver for the audio block of the g12a and sm1 SoC families. For TDMOUT's sclk to be properly inverted, bit 29 of AUDIO_CLK_TDMOUT_x_CTRL should be the inverse of bit 28. IOW bit28 == !bit29 at all times This setting is automatically applied on axg and the manual setting was added on g12a. Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20200729154359.1983085-2-jbrunet@baylibre.com

clk: let init callback return an error code

2019-12-24T02:53:13Z

If the init callback is allowed to request resources, it needs a return value to report the outcome of such a request. Signed-off-by: Jerome Brunet Link: https://lkml.kernel.org/r/20190924123954.31561-3-jbrunet@baylibre.com Reviewed-by: Andrew Lunn Acked-by: Heiko Stuebner Signed-off-by: Stephen Boyd

clk: meson: rework and clean drivers dependencies

2019-02-02T16:43:32Z

Initially, the meson clock directory only hosted 2 controllers drivers, for meson8 and gxbb. At the time, both used the same set of clock drivers so managing the dependencies was not a big concern. Since this ancient time, entropy did its job, controllers with different requirement and specific clock drivers have been added. Unfortunately, we did not do a great job at managing the dependencies between the controllers and the different clock drivers. Some drivers, such as clk-phase or vid-pll-div, are compiled even if they are useless on the target (meson8). As we are adding new controllers, we need to be able to pick a driver w/o pulling the whole thing. The patch aims to clean things up by: * providing a dedicated CONFIG_ for each clock drivers * allowing clock drivers to be compiled as a modules, if possible * stating explicitly which drivers are required by each controller. Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190201125841.26785-5-jbrunet@baylibre.com

clk: meson: add clk-phase clock driver

2018-07-09T11:47:22Z

Add a driver based meson clk-regmap to control clock phase on amlogic SoCs Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet