kernel/drivers/clk/mediatek, branch linux-5.1.y

clk: mediatek: Disable tuner_en before change PLL rate

2019-05-25T16:16:32Z

commit be17ca6ac76a5cfd07cc3a0397dd05d6929fcbbb upstream. PLLs with tuner_en bit, such as APLL1, need to disable tuner_en before apply new frequency settings, or the new frequency settings (pcw) will not be applied. The tuner_en bit will be disabled during changing PLL rate and be restored after new settings applied. Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support) Cc: Signed-off-by: Owen Chen Signed-off-by: Weiyi Lu Reviewed-by: James Liao Reviewed-by: Matthias Brugger Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: mediatek: fix clk-gate flag setting

2019-04-12T16:41:49Z

CLK_SET_RATE_PARENT would be dropped. Merge two flag setting together to correct the error. Fixes: 5a1cc4c27ad2 ("clk: mediatek: Add flags to mtk_gate") Cc: Signed-off-by: Weiyi Lu Reviewed-by: Matthias Brugger Signed-off-by: Stephen Boyd

Merge branches 'clk-typo', 'clk-json-schema', 'clk-mtk-2712-eco' and 'clk-rockchip' into clk-next

2019-03-08T18:34:22Z

- Convert a few clk bindings to JSON schema format - 3rd ECO fix for Mediatek MT2712 SoCs * clk-typo: clk: samsung: fix typo * clk-json-schema: dt-bindings: clock: Convert fixed-factor-clock to json-schema dt-bindings: clock: Convert fixed-clock binding to json-schema * clk-mtk-2712-eco: clk: mediatek: update clock driver of MT2712 dt-bindings: clock: add clock for MT2712 * clk-rockchip: clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks clk: rockchip: fix frac settings of GPLL clock for rk3328

Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk-crit' and 'clk-mtk' into clk-next

2019-03-08T18:29:30Z

* clk-ingenic: clk: ingenic: Remove set but not used variable 'enable' clk: ingenic: Fix doc of ingenic_cgu_div_info clk: ingenic: Fix round_rate misbehaving with non-integer dividers clk: ingenic: jz4740: Fix gating of UDC clock * clk-mtk-mux: clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel clk: mediatek: add MUX_GATE_FLAGS_2 * clk-qcom-sdm845-pcie: clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks * clk-mtk-crit: clk: mediatek: Mark bus and DRAM related clocks as critical clk: mediatek: Add flags to mtk_gate clk: mediatek: Add MUX_FLAGS macro * clk-mtk: clk: mediatek: correct cpu clock name for MT8173 SoC

clk: mediatek: correct cpu clock name for MT8173 SoC

2019-02-26T18:17:40Z

Correct cpu clock name from ca57 to ca72 since MT8173 does use cortex-a72. Signed-off-by: Seiya Wang Reviewed-by: Matthias Brugger Signed-off-by: Stephen Boyd

clk: mediatek: Mark bus and DRAM related clocks as critical

2019-02-26T17:54:50Z

Currently, DRAM-related clocks are not marked with CLK_IS_CRITICAL for MT6797. This causes memory corruption when the system is booted without clk_ignore_unused. This patch marks MUX ddrphycfg_sel as well as gates infra_dramc_f26m and infra_dramc_b_f26m as CLK_IS_CRITICAL. Signed-off-by: Jasper Mattsson Signed-off-by: Matthias Brugger Signed-off-by: Stephen Boyd

clk: mediatek: Add flags to mtk_gate

2019-02-26T17:53:39Z

This is required to mark gates as CLK_IS_CRITICAL. Signed-off-by: Jasper Mattsson Acked-by: Mars Cheng Signed-off-by: Matthias Brugger Signed-off-by: Stephen Boyd

clk: mediatek: Add MUX_FLAGS macro

2019-02-26T17:53:30Z

This is required to mark outputs of certain MUXes as CLK_IS_CRITICAL. Signed-off-by: Jasper Mattsson Acked-by: Mars Cheng Signed-off-by: Matthias Brugger Signed-off-by: Stephen Boyd

clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel

2019-02-25T17:19:33Z

The MUX clock of dpi1_sel should select the closet clock for itself. We could add this flag to enable this function of MUX in CCF. Signed-off-by: chunhui dai Signed-off-by: wangyan wang Signed-off-by: Stephen Boyd

clk: mediatek: add MUX_GATE_FLAGS_2

2019-02-25T17:19:32Z

Add MUX_GATE_FLAGS_2 for the clock which needs to set two falgs. Such as some mux need to set the flags of "CLK_MUX_ROUND_CLOSEST". Signed-off-by: chunhui dai Signed-off-by: wangyan wang Signed-off-by: Stephen Boyd