kernel/drivers/clk/imx/clk.h, branch linux-6.9.y

clk: imx: pllv4: Fix SPLL2 MULT range

2023-08-14T09:29:52Z

The SPLL2 on iMX8ULP is different with other frac PLLs, it can support VCO from 650Mhz to 1Ghz. According to RM, the MULT is using a range from 27 to 54, not some fixed values. If using current PLL implementation, some clock rate can't be supported. Fix the issue by adding new type for the SPLL2 and use MULT range to replace MULT table Fixes: 5f0601c47c33 ("clk: imx: Update the pllv4 to support imx8ulp") Reviewed-by: Peng Fan Reviewed-by: Jacky Bai Signed-off-by: Ye Li Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20230625123340.4067536-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa

clk: imx: drop imx_unregister_clocks

2023-05-18T14:40:22Z

There is no user using imx_unregister_clocks, so drop it. Signed-off-by: Peng Fan Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20230506090856.3599035-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa

clk: imx: imx8ulp: Add divider closest support to get more accurate clock rate

2023-04-09T14:12:49Z

If a divider's parent clock has fractional part, it will hard to round out a more accurate clock rate for this divider, add the 'CLK_DIVIDER_ROUND_CLOSEST' flags for such divider to get a more accurate clock rate. Reviewed-by: Peng Fan Signed-off-by: Jacky Bai Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20230331063814.2462059-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa

clk: imx: fracn-gppll: support integer pll

2023-04-09T13:48:54Z

The fracn gppll could be configured in FRAC or INTEGER mode during hardware design. The current driver only support FRAC mode, while this patch introduces INTEGER support. When the PLL is INTEGER pll, there is no mfn, mfd, the calculation is as below: Fvco_clk = (Fref / DIV[RDIV] ) * DIV[MFI] Fclko_odiv = Fvco_clk / DIV[ODIV] In this patch, we reuse the FRAC pll logic with some condition check to simplify the driver Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20230403095300.3386988-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa

clk: imx: drop duplicated macro

2023-04-03T20:40:14Z

Drop duplicated macro definition Signed-off-by: Peng Fan Reviewed-by: Ahmad Fatoum Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230403082728.3199849-1-peng.fan@oss.nxp.com

clk: imx: Add imx8m_clk_hw_composite_flags macro

2023-03-31T12:27:36Z

In order to set custom flags to imx8m_clk_hw_composite, split it off into a separate macro which can accept additional flags. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230323230127.120883-3-aford173@gmail.com

clk: imx: add imx_obtain_fixed_of_clock()

2023-01-31T12:45:14Z

Add imx_obtain_fixed_of_clock() to optionally add clock not configured in the devicetree. Signed-off-by: Oleksij Rempel Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230131084642.709385-15-o.rempel@pengutronix.de

clk: imx: add clk-gpr-mux driver

2023-01-31T12:45:01Z

Almost(?) every i.MX variant has clk mux for ethernet (rgmii/rmii) reference clock located in the GPR1 register. So far this clk is configured in different ways: - mach-imx6q is doing mux configuration based on ptp vs enet_ref clk comparison. - mach-imx7d is setting mux to PAD for all boards - mach-imx6ul is setting mux to internal clock for all boards. Since we have imx7d and imx6ul board variants which do not work with configurations forced by kernel mach code, we need to implement this clk mux properly as part of the clk framework. Which is done by this patch. Signed-off-by: Oleksij Rempel Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230131084642.709385-2-o.rempel@pengutronix.de

clk: imx: remove clk_count of imx_register_uart_clocks

2023-01-29T18:29:29Z

The clk count has been get with of_clk_get_parent_count, there is no need to pass clk_count from users. Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230104110032.1220721-4-peng.fan@oss.nxp.com

clk: imx: rename imx_obtain_fixed_clk_hw() to imx_get_clk_hw_by_name()

2022-11-25T09:22:15Z

The imx_obtain_fixed_clk_hw name was wrong and misleading. Renaming it to imx_get_clk_hw_by_name clarifies the purpose of the function, and will allow it to be used not only for fixed rate clocks but also in wider contexts. No functional changes intended. The replacements were made with the following command: grep -rl 'imx_obtain_fixed_clk_hw' ./ | \ xargs sed -i 's/imx_obtain_fixed_clk_hw/imx_get_clk_hw_by_name/g' Tested on a BSH SystemMaster (SMM) S2 board. Signed-off-by: Dario Binacchi Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20221113180839.1625832-1-dario.binacchi@amarulasolutions.com