kernel/drivers/clk/imx/clk-imx7ulp.c, branch linux-6.9.y

clk: imx: remove clk_count of imx_register_uart_clocks

2023-01-29T18:29:29Z

The clk count has been get with of_clk_get_parent_count, there is no need to pass clk_count from users. Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230104110032.1220721-4-peng.fan@oss.nxp.com

clk: imx: rename imx_obtain_fixed_clk_hw() to imx_get_clk_hw_by_name()

2022-11-25T09:22:15Z

The imx_obtain_fixed_clk_hw name was wrong and misleading. Renaming it to imx_get_clk_hw_by_name clarifies the purpose of the function, and will allow it to be used not only for fixed rate clocks but also in wider contexts. No functional changes intended. The replacements were made with the following command: grep -rl 'imx_obtain_fixed_clk_hw' ./ | \ xargs sed -i 's/imx_obtain_fixed_clk_hw/imx_get_clk_hw_by_name/g' Tested on a BSH SystemMaster (SMM) S2 board. Signed-off-by: Dario Binacchi Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20221113180839.1625832-1-dario.binacchi@amarulasolutions.com

clk: imx: Update the pfdv2 for 8ulp specific support

2021-09-30T13:22:56Z

On i.MX8ULP, the 'CLK_SET_RATE_PARENT' flag should NOT be set and according to the laest RM, the PFD divider value range seems will be changed in the future, so update the pfdv2 to include the specific support for i.MX8ULP. Signed-off-by: Jacky Bai Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20210914065208.3582128-8-ping.bai@nxp.com Signed-off-by: Abel Vesa

clk: imx: Update the pllv4 to support imx8ulp

2021-09-30T13:22:55Z

The PLLs used on i.MX8ULP is mostly the same as on i.MX7ULP, except the PLL register offset is changed. Change the PLLv4 driver for code reuse on i.MX7ULP and i.MX8ULP. Signed-off-by: Jacky Bai Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20210914065208.3582128-3-ping.bai@nxp.com Signed-off-by: Abel Vesa

clk: imx: Fix reparenting of UARTs not associated with stdout

2021-04-04T19:39:04Z

Most if not all i.MX SoC's call a function which enables all UARTS. This is a problem for users who need to re-parent the clock source, because any attempt to change the parent results in an busy error due to the fact that the clocks have been enabled already. clk: failed to reparent uart1 to sys_pll1_80m: -16 Instead of pre-initializing all UARTS, scan the device tree to see which UART clocks are associated to stdout, and only enable those UART clocks if it's needed early. This will move initialization of the remaining clocks until after the parenting of the clocks. When the clocks are shutdown, this mechanism will also disable any clocks that were pre-initialized. Fixes: 9461f7b33d11c ("clk: fix CLK_SET_RATE_GATE with clock rate protection") Suggested-by: Aisheng Dong Signed-off-by: Adam Ford Reviewed-by: Abel Vesa Tested-by: Ahmad Fatoum Signed-off-by: Abel Vesa

clk: imx7ulp: make it easy to change ARM core clk

2020-04-14T13:35:58Z

ARM clk could only source from divcore or hsrun_divcore. Follow what we already used on i.MX7D and i.MX8M SoCs, use imx_clk_hw_cpu API. When ARM core is running normaly, whether divcore or hwrun_divcore will finally source from SPLL_PFD0. However SPLL_PFD0 is marked with CLK_SET_GATE, so we need to disable SPLL_PFD0, when configure the rate. So add CORE and HSRUN_CORE virtual clk to make it easy to configure the clk using imx_clk_hw_cpu API. Since CORE and HSRUN_CORE already marked with CLK_IS_CRITICAL, no need to set ARM as CLK_IS_CRITICAL. And when set the rate of ARM clk, prograting it the parent with CLK_SET_RATE_PARENT will finally set the SPLL_PFD0 clk. Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Signed-off-by: Shawn Guo

clk: imx7ulp: Include clk-provider.h instead of clk.h

2020-02-17T06:33:37Z

The i.MX7ULP clock driver is provider, NOT consumer, so clk-provider.h should be used instead of clk.h. Signed-off-by: Anson Huang Reviewed-by: Stephen Boyd Signed-off-by: Shawn Guo

Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom', 'clk-freescale' and 'clk-qoriq' into clk-next

2020-01-31T21:14:26Z

- Support for Xilinx Versal platform clks - Display clk controller on qcom sc7180 - Video clk controller on qcom sc7180 - Graphics clk controller on qcom sc7180 - CPU PLLs for qcom msm8916 - Fixes for clk controllers on qcom msm8998 SoCs - Move qcom msm8974 gfx3d clk to RPM control - Display port clk support on qcom sdm845 SoCs - Global clk controller on qcom ipq6018 - Adjust composite clk to new way of describing clk parents - Add a driver for BCLK of Freescale SAI cores * clk-imx: (32 commits) clk: imx: Add support for i.MX8MP clock driver dt-bindings: imx: Add clock binding doc for i.MX8MP clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based API clk: imx: imx8mq: Switch to clk_hw based API clk: imx: imx8mm: Switch to clk_hw based API clk: imx: imx8mn: Switch to clk_hw based API clk: imx: Remove __init for imx_obtain_fixed_clk_hw() API clk: imx: gate3: Switch to clk_hw based API clk: imx: add hw API imx_clk_hw_mux2_flags clk: imx: add imx_unregister_hw_clocks clk: imx: clk-composite-8m: Switch to clk_hw based API clk: imx: clk-pll14xx: Switch to clk_hw based API clk: imx7up: Rename the clks to hws clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw based clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw based clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw based clk: imx: Rename sccg and frac pll register to suggest clk_hw clk: imx: imx7ulp composite: Rename to show is clk_hw based clk: imx: pllv2: Switch to clk_hw based API clk: imx: pllv1: Switch to clk_hw based API ... * clk-ti: clk: ti: clkctrl: Fix hidden dependency to node name clk: ti: add clkctrl data dra7 sgx clk: ti: omap5: Add missing AESS clock clk: ti: dra7: fix parent for gmac_clkctrl clk: ti: dra7: add vpe clkctrl data clk: ti: dra7: add cam clkctrl data dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock * clk-xilinx: clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag clk: zynqmp: Fix divider calculation clk: zynqmp: Add support for get max divider clk: zynqmp: Warn user if clock user are more than allowed clk: zynqmp: Extend driver for versal dt-bindings: clock: Add bindings for versal clock driver * clk-nvidia: clk: tegra20/30: Explicitly set parent clock for Video Decoder clk: tegra20/30: Don't pre-initialize displays parent clock clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe() clk: tegra: Mark fuse clock as critical * clk-qcom: (35 commits) clk: qcom: rpmh: Sort OF match table dt-bindings: fix warnings in validation of qcom,gcc.yaml dt-binding: fix compilation error of the example in qcom,gcc.yaml clk: qcom: Add ipq6018 Global Clock Controller support clk: qcom: Add DT bindings for ipq6018 gcc clock controller clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks clk: qcom: rpmh: Add IPA clock for SC7180 clk: qcom: rpmh: skip undefined clocks when registering clk: qcom: Add video clock controller driver for SC7180 dt-bindings: clock: Introduce SC7180 QCOM Video clock bindings dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings clk: qcom: Add graphics clock controller driver for SC7180 dt-bindings: clock: Introduce SC7180 QCOM Graphics clock bindings dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings clk: qcom: apcs-msm8916: use clk_parent_data to specify the parent clk: qcom: Add display clock controller driver for SC7180 dt-bindings: clock: Introduce QCOM sc7180 display clock bindings dt-bindings: clock: Add YAML schemas for the QCOM DISPCC clock bindings clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration clk: qcom: alpha-pll: Remove useless read from set rate ... * clk-freescale: clk: fsl-sai: new driver dt-bindings: clock: document the fsl-sai driver clk: composite: add _register_composite_pdata() variants * clk-qoriq: clk: qoriq: add ls1088a hwaccel clocks support clk: ls1028a: Add clock driver for Display output interface dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings

clk: imx7up: Rename the clks to hws

2019-12-11T11:20:03Z

This is just to keep in line with the other i.MX clock drivers that are clk_hw based. Plus, it makes more sense to be called hws since its type is clk_hw not clk. Signed-off-by: Abel Vesa Reviewed-by: Peng Fan Signed-off-by: Shawn Guo

clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw based

2019-12-11T11:19:59Z

Renaming the imx_clk_divider_gate register function to imx_clk_hw_divider_gate to be more obvious it is clk_hw based. Signed-off-by: Abel Vesa Reviewed-by: Peng Fan Signed-off-by: Shawn Guo