kernel/drivers/clk/imx/clk-composite-7ulp.c, branch linux-6.9.y

clk: imx: Remove values for mmask and nmask in struct clk_fractional_divider

2023-04-05T19:09:27Z

Now that fractional_divider clk computes mmask and nmask when needed, there is no more need to provide them explicitly anymore. Signed-off-by: Christophe JAILLET Link: https://lore.kernel.org/r/187a2266c3a034a593a151d6e5e6b21118043b5d.1680423909.git.christophe.jaillet@wanadoo.fr Reviewed-by: Abel Vesa Signed-off-by: Stephen Boyd

clk: imx: Fix the build break when clk-imx8ulp build as module

2021-10-01T07:15:42Z

Export the necessary symbols to fix the build break when clk-imx8ulp build as module Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp") Signed-off-by: Jacky Bai Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20210917061629.3798360-1-ping.bai@nxp.com Signed-off-by: Abel Vesa

clk: imx: Add the pcc reset controller support on imx8ulp

2021-09-30T13:22:56Z

On i.MX8ULP, for some of the PCCs, it has a peripheral SW RST bit resides in the same registers as the clock controller. So add this SW RST controller support alongs with the pcc clock initialization. the reset and clock shared the same register, to avoid accessing the same register by reset control and clock control concurrently, locking is necessary, so reuse the imx_ccm_lock spinlock to simplify the code. Suggested-by: Liu Ying Signed-off-by: Jacky Bai Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20210914065208.3582128-10-ping.bai@nxp.com Signed-off-by: Abel Vesa

clk: imx: Add 'CLK_SET_RATE_NO_REPARENT' for composite-7ulp

2021-09-30T13:22:55Z

For the imx_composite-7ulp clock type, The clock parent should be changed explicitly by end user of this clock, if the the 'CLK_SET_RATE_NO_REPARENT' flag is not set, when user want to set a clock frequency that can NOT get from HW accurately, then the clock's parent will be switch to another clock parent sometimes. This is NOT what we expected and introduced some additional debug effort, so add the 'CLK_SET_RATE_NO_REPARENT' to avoid such unexpected result. Signed-off-by: Jacky Bai Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20210914065208.3582128-6-ping.bai@nxp.com Signed-off-by: Abel Vesa

clk: imx: disable i.mx7ulp composite clock during initialization

2021-09-30T13:22:55Z

i.MX7ULP peripheral clock ONLY allow parent/rate to be changed with clock gated, however, during clock tree initialization, the peripheral clock could be enabled by bootloader, but the prepare count in clock tree is still zero, so clock core driver will allow parent/rate changed even with CLK_SET_RATE_GATE/CLK_SET_PARENT_GATE set, but the change will fail due to HW NOT allow parent/rate change with clock enabled. It will cause clock HW status mismatch with clock tree info and lead to function issue. Below is an example: usdhc0's pcc clock value is 0xC5000000 during kernel boot up, it means usdhc0 clock is enabled, its parent is APLL_PFD1. In DT file, the usdhc0 clock settings are as below: assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>; when kernel boot up, the clock tree info is as below, but the usdhc0 PCC register is still 0xC5000000, which means its parent is still from APLL_PFD1, which is incorrect and cause usdhc0 NOT work. nic1_clk 2 2 0 176000000 0 0 50000 usdhc0 0 0 0 176000000 0 0 50000 After making sure the peripheral clock is disabled during clock tree initialization, the usdhc0 is working, and this change is necessary for all i.MX7ULP peripheral clocks. Signed-off-by: Anson Huang Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20210914065208.3582128-5-ping.bai@nxp.com Signed-off-by: Abel Vesa

clk: imx: Update the compsite driver to support imx8ulp

2021-09-30T13:22:55Z

On i.MX8ULP, some peripherals have a sw_rst control resides in the per device PCC clock control register, all others are same as i.MX7ULP, so update the 7ulp clock composite driver to support i.MX8ULP to maxmimize the code reuse. Signed-off-by: Peng Fan Signed-off-by: Jacky Bai Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20210914065208.3582128-4-ping.bai@nxp.com Signed-off-by: Abel Vesa

clk: fractional-divider: Hide clk_fractional_divider_ops from wide audience

2021-08-12T19:42:00Z

The providers are all located in drivers/clk/ and hence no need to export the clock operations to wider audience. Hide them by moving to drivers/clk/clk-fractional-divider.h. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20210812170025.67074-2-andriy.shevchenko@linux.intel.com Signed-off-by: Stephen Boyd

clk: imx: Explicitly include bits.h

2020-08-22T12:36:57Z

It is better to explicitly include the required header file rather then get it through some recursive include. Signed-off-by: Anson Huang Acked-by: Stephen Boyd Signed-off-by: Shawn Guo

clk: imx: imx7ulp composite: Rename to show is clk_hw based

2019-12-11T11:19:48Z

Renaming the imx7ulp_clk_composite register function to imx7ulp_clk_hw_composite to show it is clk_hw based. Signed-off-by: Abel Vesa Reviewed-by: Peng Fan Signed-off-by: Shawn Guo

clk: imx: add imx7ulp composite clk support

2018-12-03T19:31:36Z

The imx composite clk is designed for Peripheral Clock Control (PCC) module observed in IMX ULP SoC series. NOTE pcc can only be operated when clk is gated. Cc: Stephen Boyd Cc: Michael Turquette Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by: Dong Aisheng [sboyd@kernel.org: Include clk.h for sparse warnings] Signed-off-by: Stephen Boyd