kernel/drivers/clk/imx/Makefile, branch linux-6.9.y

clk: imx: imx8: add audio clock mux driver

2023-08-14T09:27:52Z

The Audio Clock Mux (ACM) is a collection of control registers and multiplexers that are used to route the audio source clocks to the audio peripherals. Each audio peripheral has its dedicated audio clock mux (which differ based on usage) and control register. Signed-off-by: Shengjiu Wang Reviewed-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/1690260984-25744-3-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Abel Vesa

clk: imx: imx8mp: Add audiomix block control

2023-03-31T12:03:19Z

Unlike the other block control IPs in i.MX8M, the audiomix is mostly a series of clock gates and muxes. Model it as a large static table of gates and muxes with one exception, which is the PLL14xx . The PLL14xx SAI PLL has to be registered separately. Reviewed-by: Marco Felsch Reviewed-by: Peng Fan Reviewed-by: Fabio Estevam Tested-by: Adam Ford #imx8mp-beacon-kit Tested-by: Alexander Stein Tested-by: Luca Ceresoli Signed-off-by: Marek Vasut Tested-by: Richard Leitner Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230301163257.49005-2-marex@denx.de

clk: imx: add clk-gpr-mux driver

2023-01-31T12:45:01Z

Almost(?) every i.MX variant has clk mux for ethernet (rgmii/rmii) reference clock located in the GPR1 register. So far this clk is configured in different ways: - mach-imx6q is doing mux configuration based on ptp vs enet_ref clk comparison. - mach-imx7d is setting mux to PAD for all boards - mach-imx6ul is setting mux to internal clock for all boards. Since we have imx7d and imx6ul board variants which do not work with configurations forced by kernel mach code, we need to implement this clk mux properly as part of the clk framework. Which is done by this patch. Signed-off-by: Oleksij Rempel Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230131084642.709385-2-o.rempel@pengutronix.de

clk: imx: add i.MX93 clk gate

2022-09-19T10:06:45Z

i.MX93 LPCG is different from i.MX8M CCGR. Although imx_clk_hw_gate4_flags is used here, it not strictly match i.MX93. i.MX93 has such design: - LPCG_DIRECT use BIT0 as on/off gate when LPCG_AUTHEN CPU_LPM is 0 - LPCG_LPM_CUR use BIT[2:0] as on/off gate when LPCG_AUTHEN CPU_LPM is 1 The current implementation suppose CPU_LPM is 0, and use LPCG_DIRECT BIT[1:0] as on/off gate. Although BIT1 is touched, actually BIT1 is reserved. And imx_clk_hw_gate4_flags use mask 0x3 to determine whether the clk is enabled or not, but i.MX93 LPCG only use BIT0 to control when CPU_LPM is 0. So clk disabled unused during kernel boot not able to gate off the unused clocks. To match i.MX93 LPCG, introduce imx93_clk_gate. Signed-off-by: Peng Fan Reviewed-by: Ye Li Reviewed-by: Jacky Bai Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20220830033137.4149542-6-peng.fan@oss.nxp.com

clk: imx: add i.MX93 clk

2022-03-04T15:06:29Z

Add i.MX93 clk driver. i.MX93 clk hardware design is different compared with i.MX8M. It supports 4 sources for each clk root and the sources are separated into a few groups, low speed/fast io/audio and etc. Reviewed-by: Abel Vesa Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20220228020908.2810346-6-peng.fan@oss.nxp.com [abel.vesa@nxp.com: Added missing module license and description] Signed-off-by: Abel Vesa

clk: imx: support fracn gppll

2022-03-04T15:06:29Z

This PLL module is a Fractional-N synthesizer, supporting 30-bit numerator and denominator. Numerator is a signed number. It has feature to adjust fractional portion of feedback divider dynamically. This fracn gppll is used in i.MX93. Reviewed-by: Abel Vesa Reviewed-by: Sascha Hauer Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20220228020908.2810346-5-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa

clk: imx: add i.MX93 composite clk

2022-03-04T15:06:29Z

i.MX93 CCM ROOT clock has a mux, gate and divider in one register, here is to combine all these into one composite clk and simplify clk tree. i.MX93 CCM is a new IP compared with i.MX8M, so introduce a new file. Reviewed-by: Abel Vesa Reviewed-by: Stephen Boyd Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20220228020908.2810346-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa

clk: imx: Add imx8dxl clk driver

2022-01-29T13:12:07Z

Add files for imx8dxl clk driver which is based on imx8qxp clock driver. Signed-off-by: Jacky Bai Signed-off-by: Abel Vesa Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/1639747533-9778-1-git-send-email-abel.vesa@nxp.com

clk: imx: Add initial support for i.MXRT1050 clock driver

2022-01-29T13:12:06Z

Add clock driver support for i.MXRT1050. Signed-off-by: Jesse Taube Suggested-by: Giulio Benetti Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20220111215415.2075257-6-Mr.Bossman075@gmail.com Signed-off-by: Abel Vesa

clk: imx: Add clock driver for imx8ulp

2021-09-30T13:22:56Z

Add clock driver for i.MX8ULP. Signed-off-by: Peng Fan Signed-off-by: Jacky Bai Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20210914065208.3582128-9-ping.bai@nxp.com Signed-off-by: Abel Vesa