kernel/drivers/clk/clk.c, branch 0x221E-v0.0.1-v6.19

clk: Use hashtable for global clk lookups

2025-09-21T17:15:43Z

A clk lookup using clk_core_lookup() is currently somewhat expensive since it has to walk the whole clk tree to find a match. This is extremely bad in the clk_core_init() function where it is used to look for clk name conflicts, which is always the worst case of walking the whole tree. Moreover, the number of clks checked increases as more clks are registered, causing each subsequent clk registration becoming slower. Add a hashtable for doing clk lookups to replace the tree walk method. On arm64 this increases kernel memory usage by 4 KB for the hashtable, and 16 bytes (2 pointers) for |struct hlist_node| in each clk. On a platform with around 800 clks, this reduces the time spent in clk_core_lookup() significantly: | PID 0 | kworker | | before | after | before | after | ------------------------------------------- avg | 203 us | 2.7 us | 123 us | 1.5 us | ------------------------------------------- min | 4.7 us | 2.3 us | 102 us | 0.9 us | ------------------------------------------- max | 867 us | 4.8 us | 237 us | 3.5 us | ------------------------------------------- culm | 109 ms | 1.5 ms | 21 ms | 0.3 ms | This in turn reduces the time spent in clk_hw_register(), and ultimately, boot time. On a different system with close to 700 clks, This reduces boot time by around 110 ms. While this doesn't seem like a lot, this helps in cases where minimizing boot time is important. Signed-off-by: Chen-Yu Tsai Tested-by: Brian Masney Reviewed-by: Brian Masney Signed-off-by: Stephen Boyd

clk: Sort include statements

2025-09-21T17:15:37Z

The clk core has its include statements in some random order. Clean it up before we add more. Signed-off-by: Chen-Yu Tsai Reviewed-by: Brian Masney Signed-off-by: Stephen Boyd

clk: add a clk_hw helpers to get the clock device or device_node

2025-06-20T01:25:48Z

Add helpers to get the device or device_node associated with clk_hw. This can be used by clock drivers to access various device related functionality such as devres, dev_ prints, etc ... Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20250417-clk-hw-get-helpers-v1-1-7743e509612a@baylibre.com Reviewed-by: Brian Masney Signed-off-by: Stephen Boyd

Merge branches 'clk-parent', 'clk-renesas', 'clk-mediatek' and 'clk-cleanup' into clk-next

2025-03-26T18:26:26Z

* clk-parent: clk: check for disabled clock-provider in of_clk_get_hw_from_clkspec() * clk-renesas: (24 commits) clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1 clk: renesas: r7s9210: Distinguish clocks by clock type clk: renesas: rzg2l: Remove unneeded nullify checks clk: renesas: cpg-mssr: Remove obsolete nullify check clk: renesas: r9a09g057: Add entries for the DMACs clk: renesas: r9a09g047: Add CANFD clocks and resets clk: renesas: r9a09g047: Add CRU0 clocks and resets clk: renesas: rzv2h: Update error message clk: renesas: rzg2l: Update error message clk: renesas: r9a09g047: Add ICU clock/reset clk: renesas: r9a07g043: Fix HP clock source for RZ/Five clk: renesas: r9a09g047: Add SDHI clocks/resets clk: renesas: r8a779h0: Add VSPX clock clk: renesas: r8a779h0: Add FCPVX clock clk: renesas: r8a08g045: Check the source of the CPU PLL settings clk: renesas: r9a09g047: Add WDT clocks and resets clk: renesas: r8a779h0: Add ISP core clocks clk: renesas: r8a779g0: Add ISP core clocks clk: renesas: r8a779a0: Add ISP core clocks ... * clk-mediatek: clk: mediatek: Add SMI LARBs reset for MT8188 dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188 clk: mediatek: mt8188-vdo1: Add VDO1_DPI1_HDMI clock for hdmitx dt-bindings: clock: mediatek,mt8188: Add VDO1_DPI1_HDMI clock * clk-cleanup: dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatibles clk: davinci: remove support for da830 dt-bindings: clock: ti: Convert ti-clkctrl.txt to json-schema clk: mmp: Fix NULL vs IS_ERR() check clk: Print an error when clk registration fails clk: Correct the data types of the variables in clk_calc_new_rates clk: imgtec: use %pe for better readability of errors while printing clk: stm32f4: fix an uninitialized variable clk: keystone: syscon-clk: Do not use syscon helper to build regmap

clk: Print an error when clk registration fails

2025-03-04T21:53:48Z

We have a lot of driver code that prints an error message when registering a clk fails. Do that in the core function instead to consolidate code. This also helps drivers avoid the anti-pattern of accessing the struct clk_hw::init pointer after registration. Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20250226235408.1339266-1-sboyd@kernel.org

clk: Correct the data types of the variables in clk_calc_new_rates

2025-03-04T20:59:06Z

In clk_calc_new_rates, the "ret" is only used to store the return value of clk_core_determine_round_nolock, and the data type of the return value of clk_core_determine_round_nolock is int. Signed-off-by: Chuan Liu Link: https://lore.kernel.org/r/20250207-correct_data_types-v1-1-f22bc7ea220d@amlogic.com Signed-off-by: Stephen Boyd

clk: check for disabled clock-provider in of_clk_get_hw_from_clkspec()

2025-02-26T22:33:15Z

of_clk_get_hw_from_clkspec() checks all available clock-providers by comparing their of nodes to the one from the clkspec. If no matching clock provider is found, the function returns -EPROBE_DEFER to cause a re-check at a later date. If a matching clock provider is found, an authoritative answer can be retrieved from it whether the clock exists or not. This does not take into account that the clock-provider may never appear, because it's node is disabled. This can happen when a clock is optional, provided by a separate block which never gets enabled. One example of this happening is the rk3588's VOP, which has optional additional display clocks coming from PLLs inside the hdmiphy blocks. These can be used for better rates, but the system will also work without them. The problem around that is described in the followups to[1]. As we already know the of node of the presumed clock provider, add a check via of_device_is_available() whether this is a "valid" device node. This prevents eternal defer loops. Link: https://lore.kernel.org/dri-devel/20250215-vop2-hdmi1-disp-modes-v1-3-81962a7151d6@collabora.com/ [1] Reviewed-by: Sebastian Reichel Tested-by: Cristian Ciocaltea Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250222223733.2990179-1-heiko@sntech.de [sboyd@kernel.org: Reword commit text a bit] Signed-off-by: Stephen Boyd

Merge branches 'clk-airoha', 'clk-rockchip', 'clk-stm', 'clk-thead' and 'clk-bcm' into clk-next

2025-01-21T19:22:26Z

* clk-airoha: clk: en7523: Add clock for eMMC for EN7581 dt-bindings: clock: add ID for eMMC for EN7581 dt-bindings: clock: drop NUM_CLOCKS define for EN7581 clk: en7523: Rework clock handling for different clock numbers clk: en7523: Initialize num before accessing hws in en7523_register_clocks() clk: en7523: Fix wrong BUS clock for EN7581 clk: amlogic: axg-audio: revert reset implementation Revert "clk: Fix invalid execution of clk_set_rate" * clk-rockchip: clk: rockchip: rk3588: make refclko25m_ethX critical clk: rockchip: rk3588: drop RK3588_LINKED_CLK clk: rockchip: implement linked gate clock support clk: rockchip: expose rockchip_clk_set_lookup clk: rockchip: rk3588: register GATE_LINK later clk: rockchip: support clocks registered late * clk-stm: clk: stm32f4: support spread spectrum clock generation clk: stm32f4: use FIELD helpers to access the PLLCFGR fields dt-bindings: clock: st,stm32-rcc: support spread spectrum clocking dt-bindings: clock: convert stm32 rcc bindings to json-schema * clk-thead: clk: thead: Fix cpu2vp_clk for TH1520 AP_SUBSYS clocks clk: thead: Add CLK_IGNORE_UNUSED to fix TH1520 boot clk: thead: Fix clk gate registration to pass flags * clk-bcm: clk: bcm: rpi: Add disp clock clk: bcm: rpi: Create helper to retrieve private data clk: bcm: rpi: Enable minimize for all firmware clocks clk: bcm: rpi: Allow cpufreq driver to also adjust gpu clocks clk: bcm: rpi: Add ISP to exported clocks

clk: fix an OF node reference leak in of_clk_get_parent_name()

2024-12-10T22:53:49Z

Current implementation of of_clk_get_parent_name() leaks an OF node reference on error path. Add a of_node_put() call before returning an error. This bug was found by an experimental static analysis tool that I am developing. Fixes: 8da411cc1964 ("clk: let of_clk_get_parent_name() fail for invalid clock-indices") Signed-off-by: Joe Hattori Link: https://lore.kernel.org/r/20241210130913.3615205-1-joe@pf.is.s.u-tokyo.ac.jp Signed-off-by: Stephen Boyd

Revert "clk: Fix invalid execution of clk_set_rate"

2024-12-03T01:20:12Z

This reverts commit 25f1c96a0e841013647d788d4598e364e5c2ebb7. The offending commit results in errors like cpu cpu0: _opp_config_clk_single: failed to set clock rate: -22 spamming the logs on the Lenovo ThinkPad X13s and other Qualcomm machines when cpufreq tries to update the CPUFreq HW Engine clocks. As mentioned in commit 4370232c727b ("cpufreq: qcom-hw: Add CPU clock provider support"): [T]he frequency supplied by the driver is the actual frequency that comes out of the EPSS/OSM block after the DCVS operation. This frequency is not same as what the CPUFreq framework has set but it is the one that gets supplied to the CPUs after throttling by LMh. which seems to suggest that the driver relies on the previous behaviour of clk_set_rate(). Since this affects many Qualcomm machines, let's revert for now. Fixes: 25f1c96a0e84 ("clk: Fix invalid execution of clk_set_rate") Reported-by: Aishwarya TCV Link: https://lore.kernel.org/all/e2d83e57-ad07-411b-99f6-a4fc3c4534fa@arm.com/ Cc: Chuan Liu Cc: Manivannan Sadhasivam Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20241202100621.29209-1-johan+linaro@kernel.org Signed-off-by: Stephen Boyd