kernel/drivers/ata/libahci.c, branch linux-5.1.y

ata: libahci: Only warn for AHCI_HFLAG_MULTI_MSI set when genuine custom irq handler implemented

2019-02-28T21:07:48Z

For an AHCI controller with AHCI_HFLAG_MULTI_MSI flag set, we may get the following log, regardless of whether a custom irq handler was implemented or not: [ 14.700238] ahci 0000:74:03.0: both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented This is because we can set hpriv->irq_handler to ahci_single_level_irq_intr() if not already set, in ahci_init_one()->ahci_pci_save_initial_config()->ahci_save_initial_config(). Stop having this warn being misleading by adding a check for hpriv->irq_handler != ahci_single_level_irq_intr. Signed-off-by: John Garry Signed-off-by: Jens Axboe

Merge branch 'for-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata

2018-08-24T20:20:33Z

Pull libata updates from Tejun Heo: "Nothing too interesting. Mostly ahci and ahci_platform changes, many around power management" * 'for-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: (22 commits) ata: ahci_platform: enable to get and control reset ata: libahci_platform: add reset control support ata: add an extra argument to ahci_platform_get_resources() ata: sata_rcar: Add r8a77965 support ata: sata_rcar: exclude setting of PHY registers in Gen3 ata: sata_rcar: really mask all interrupts on Gen2 and later Revert "ata: ahci_platform: allow disabling of hotplug to save power" ata: libahci: Allow reconfigure of DEVSLP register ata: libahci: Correct setting of DEVSLP register ata: ahci: Enable DEVSLP by default on x86 with SLP_S0 ata: ahci: Support state with min power but Partial low power state Revert "ata: ahci_platform: convert kcalloc to devm_kcalloc" ata: sata_rcar: Add rudimentary Runtime PM support ata: sata_rcar: Provide a short-hand for &pdev->dev ata: Only output sg element mapped number in verbose debug ata: Guard ata_scsi_dump_cdb() by ATA_VERBOSE_DEBUG ata: ahci_platform: convert kcalloc to devm_kcalloc ata: ahci_platform: convert kzallloc to kcalloc ata: ahci_platform: correct parameter documentation for ahci_platform_shutdown libata: remove ata_sff_data_xfer_noirq() ...

ata: libahci: Allow reconfigure of DEVSLP register

2018-07-30T17:33:18Z

There are two modes in which DEVSLP can be entered. The OS initiated or hardware autonomous. In hardware autonomous mode, BIOS configures the AHCI controller and the device to enable DEVSLP. But they may not be ideal for all cases. So in this case, OS should be able to reconfigure DEVSLP register. Currently if the DEVSLP is already enabled, we can't set again as it will simply return. There are some systems where the firmware is setting high DITO by default, in this case we can't modify here to correct settings. With the default in several seconds, we are not able to transition to DEVSLP. This change will allow reconfiguration of devslp register if DITO is different. Signed-off-by: Srinivas Pandruvada Reviewed-by: Hans de Goede Signed-off-by: Tejun Heo

ata: libahci: Correct setting of DEVSLP register

2018-07-30T17:32:51Z

We have seen that on some platforms, SATA device never show any DEVSLP residency. This prevent power gating of SATA IP, which prevent system to transition to low power mode in systems with SLP_S0 aka modern standby systems. The PHY logic is off only in DEVSLP not in slumber. Reference: https://www.intel.com/content/dam/www/public/us/en/documents/datasheets /332995-skylake-i-o-platform-datasheet-volume-1.pdf Section 28.7.6.1 Here driver is trying to do read-modify-write the devslp register. But not resetting the bits for which this driver will modify values (DITO, MDAT and DETO). So simply reset those bits before updating to new values. Signed-off-by: Srinivas Pandruvada Reviewed-by: Rafael J. Wysocki Reviewed-by: Hans de Goede Signed-off-by: Tejun Heo

ata: ahci: Support state with min power but Partial low power state

2018-07-30T14:09:10Z

Currently when min_power policy is selected, the partial low power state is not entered and link will try aggressively enter to only slumber state. Add a new policy which still enable DEVSLP but also try to enter partial low power state. This policy is presented as "min_power_with_partial". For information the difference between partial and slumber Partial – PHY logic is powered up, and in a reduced power state. The link PM exit latency to active state maximum is 10 ns. Slumber – PHY logic is powered up, and in a reduced power state. The link PM exit latency to active state maximum is 10 ms. Devslp – PHY logic is powered down. The link PM exit latency from this state to active state maximum is 20 ms, unless otherwise specified by DETO. Suggested-and-reviewed-by: Hans de Goede Signed-off-by: Srinivas Pandruvada Signed-off-by: Tejun Heo

libahci: Fix possible Spectre-v1 pmp indexing in ahci_led_store()

2018-06-18T18:04:28Z

Currently smatch warns of possible Spectre-V1 issue in ahci_led_store(): drivers/ata/libahci.c:1150 ahci_led_store() warn: potential spectre issue 'pp->em_priv' (local cap) Userspace controls @pmp from following callchain: em_message->store() ->ata_scsi_em_message_store() -->ap->ops->em_store() --->ahci_led_store() After the mask+shift @pmp is effectively an 8b value, which is used to index into an array of length 8, so sanitize the array index. Signed-off-by: John Garry Signed-off-by: Tejun Heo

ata: ahci: rpm_put port on port_stop to match rpm_get in port_start

2018-06-18T17:58:42Z

This change balances out the final ahci_port_resume in port_start to ensure reference counts are correct after port stop. Signed-off-by: Samuel Morris Signed-off-by: Tejun Heo

Merge branch 'for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata

2018-06-06T00:01:41Z

Pull libata updates from Tejun Heo: - libata has always been limiting the maximum queue depth to 31, with one entry set aside mostly for historical reasons. This didn't use to make much difference but Jens found out that modern hard drives can actually perform measurably better with the extra one queue depth. Jens updated libata core so that it can make use of full 32 queue depth - Damien updated command retry logic in error handling so that it doesn't unnecessarily retry when upper layer (SCSI) is gonna handle them - A couple misc changes * 'for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: sata_fsl: use the right type for tag bitshift ahci: enable full queue depth of 32 libata: don't clamp queue depth to ATA_MAX_QUEUE - 1 libata: add extra internal command sata_nv: set host can_queue count appropriately libata: remove assumption that ATA_MAX_QUEUE - 1 is the max libata: use ata_tag_internal() consistently libata: bump ->qc_active to a 64-bit type libata: convert core and drivers to ->hw_tag usage libata: introduce notion of separate hardware tags libata: Fix command retry decision libata: Honor RQF_QUIET flag libata: Make ata_dev_set_mode() less verbose libata: Fix ata_err_string() libata: Fix comment typo in ata_eh_analyze_tf() sata_nv: don't use block layer bounce buffer ata: hpt37x: Convert to use match_string() helper

libata: convert core and drivers to ->hw_tag usage

2018-05-11T20:10:43Z

Anything that goes to the hardware should use ->hw_tag, anything related to internal lookup should be using ->tag. Signed-off-by: Jens Axboe Signed-off-by: Tejun Heo

libahci: Allow drivers to override stop_engine

2018-04-26T18:25:04Z

Marvell armada37xx, armada7k and armada8k share the same AHCI sata controller IP, and currently there is an issue (Errata Ref#226)that the SATA can not be detected via SATA Port-MultiPlayer(PMP). After debugging, the reason is found that the value of Port-x FIS-based Switching Control (PxFBS@0x40) became wrong. According to design, the bits[11:8, 0] of register PxFBS are cleared when Port Command and Status (0x18) bit[0] changes its value from 1 to 0, i.e. falling edge of Port Command and Status bit[0] sends PULSE that resets PxFBS bits[11:8; 0]. So it needs save the port PxFBS register before PxCMD ST write and restore the port PxFBS register afterwards in ahci_stop_engine(). This commit allows drivers to override ahci_stop_engine behavior for use by the Marvell AHCI driver(and potentially other drivers in the future). Signed-off-by: Evan Wang Cc: Ofer Heifetz Cc: Tejun Heo Cc: Thomas Petazzoni Signed-off-by: Tejun Heo