kernel/arch/xtensa/include/asm/pgtable.h, branch linux-5.1.y

xtensa: platform-specific handling of coherent memory

2018-07-11T22:59:41Z

Memory layout is not fixed for noMMU xtensa configurations. Platforms that need to use coherent DMA should implement platform_vaddr_* helpers that check address type (cached/uncached) and convert addresses between these types. Signed-off-by: Max Filippov

xtensa: add support for KASAN

2017-12-17T06:37:12Z

Cover kernel addresses above 0x90000000 by the shadow map. Enable HAVE_ARCH_KASAN when MMU is enabled. Provide kasan_early_init that fills shadow map with writable copies of kasan_zero_page. Call kasan_early_init right after mmu initialization in the setup_arch. Provide kasan_init that allocates proper shadow map pages from the memblock and puts these pages into the shadow map for addresses from VMALLOC area to the end of KSEG. Call kasan_init right after memblock initialization. Don't use KASAN for the boot code, MMU and KASAN initialization and page fault handler. Make kernel stack size 4 times larger when KASAN is enabled to avoid stack overflows. GCC 7.3, 8 or newer is required to build the xtensa kernel with KASAN. Signed-off-by: Max Filippov

arch, mm: convert all architectures to use 5level-fixup.h

2017-03-09T19:48:47Z

If an architecture uses 4level-fixup.h we don't need to do anything as it includes 5level-fixup.h. If an architecture uses pgtable-nop*d.h, define __ARCH_USE_5LEVEL_HACK before inclusion of the header. It makes asm-generic code to use 5level-fixup.h. If an architecture has 4-level paging or folds levels on its own, include 5level-fixup.h directly. Signed-off-by: Kirill A. Shutemov Acked-by: Michal Hocko Signed-off-by: Linus Torvalds

xtensa: move kernel mapping addresses into kmem_layout.h

2016-07-24T03:33:57Z

Create a header dedicated to memory layout definitions. Include it from places where these definitions are needed. Express vmalloc area address, VIRTUAL_MEMORY_ADDRESS and KERNELOFFSET through KSEG address. Signed-off-by: Max Filippov

xtensa: nommu: fix USER_RING definition

2015-11-02T15:02:58Z

There's no kernel/user separation in noMMU and PS.RING may not exist. Even if it exists it should not be used because TLB entries are not set up for user ring on user pages. Signed-off-by: Max Filippov

mm: make FIRST_USER_ADDRESS unsigned long on all archs

2015-02-12T01:06:03Z

LKP has triggered a compiler warning after my recent patch "mm: account pmd page tables to the process": mm/mmap.c: In function 'exit_mmap': >> mm/mmap.c:2857:2: warning: right shift count >= width of type [enabled by default] The code: > 2857 WARN_ON(mm_nr_pmds(mm) > 2858 round_up(FIRST_USER_ADDRESS, PUD_SIZE) >> PUD_SHIFT); In this, on tile, we have FIRST_USER_ADDRESS defined as 0. round_up() has the same type -- int. PUD_SHIFT. I think the best way to fix it is to define FIRST_USER_ADDRESS as unsigned long. On every arch for consistency. Signed-off-by: Kirill A. Shutemov Reported-by: Wu Fengguang Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

xtensa: drop _PAGE_FILE and pte_file()-related helpers

2015-02-10T22:30:33Z

We've replaced remap_file_pages(2) implementation with emulation. Nobody creates non-linear mapping anymore. Signed-off-by: Kirill A. Shutemov Acked-by: Max Filippov Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

xtensa: nommu: provide _PAGE_CHG_MASK definition

2014-10-21T09:28:46Z

Signed-off-by: Max Filippov

xtensa: implement pgprot_noncached

2014-10-05T23:23:50Z

The default pgprot_noncached doesn't do anything. This leads to issues when drivers rely on it to disable caching in userspace mappings. Implement pgprot_noncached properly so that caching of userspace mappings could be controlled. Signed-off-by: Max Filippov

xtensa: fix TLBTEMP_BASE_2 region handling in fast_second_level_miss

2014-08-14T07:59:19Z

Current definition of TLBTEMP_BASE_2 is always 32K above the TLBTEMP_BASE_1, whereas fast_second_level_miss handler for the TLBTEMP region analyzes virtual address bit (PAGE_SHIFT + DCACHE_ALIAS_ORDER) to determine TLBTEMP region where the fault happened. The size of the TLBTEMP region is also checked incorrectly: not 64K, but twice data cache way size (whicht may as well be less than the instruction cache way size). Fix TLBTEMP_BASE_2 to be TLBTEMP_BASE_1 + data cache way size. Provide TLBTEMP_SIZE that is a greater of doubled data cache way size or the instruction cache way size, and use it to determine if the second level TLB miss occured in the TLBTEMP region. Practical occurence of page faults in the TLBTEMP area is extremely rare, this code can be tested by deletion of all w[di]tlb instructions in the tlbtemp_mapping region. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov