<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/arch/xtensa/include/asm/cmpxchg.h, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
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<updated>2025-06-06T08:03:35Z</updated>
<entry>
<title>xtensa: Replace __ASSEMBLY__ with __ASSEMBLER__ in non-uapi headers</title>
<updated>2025-06-06T08:03:35Z</updated>
<author>
<name>Thomas Huth</name>
<email>thuth@redhat.com</email>
</author>
<published>2025-03-14T07:10:10Z</published>
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<id>urn:sha1:44a4ef59d5506c6dc7599d876a3a1014697ec480</id>
<content type='text'>
While the GCC and Clang compilers already define __ASSEMBLER__
automatically when compiling assembly code, __ASSEMBLY__ is a
macro that only gets defined by the Makefiles in the kernel.
This can be very confusing when switching between userspace
and kernelspace coding, or when dealing with uapi headers that
rather should use __ASSEMBLER__ instead. So let's standardize on
the __ASSEMBLER__ macro that is provided by the compilers now.

This is a completely mechanical patch (done with a simple "sed -i"
statement).

Cc: Chris Zankel &lt;chris@zankel.net&gt;
Cc: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
Signed-off-by: Thomas Huth &lt;thuth@redhat.com&gt;
Message-Id: &lt;20250314071013.1575167-40-thuth@redhat.com&gt;
Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: Emulate one-byte cmpxchg</title>
<updated>2024-09-13T14:10:38Z</updated>
<author>
<name>Paul E. McKenney</name>
<email>paulmck@kernel.org</email>
</author>
<published>2024-03-27T22:28:04Z</published>
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<id>urn:sha1:e799bef0d9c85b963938d8f31806a898385a5b09</id>
<content type='text'>
Use the new cmpxchg_emu_u8() to emulate one-byte cmpxchg() on xtensa.

[ paulmck: Apply kernel test robot feedback. ]
[ paulmck: Drop two-byte support per Arnd Bergmann feedback. ]
[ Apply Geert Uytterhoeven feedback. ]

Signed-off-by: Paul E. McKenney &lt;paulmck@kernel.org&gt;
Tested-by: Yujie Liu &lt;yujie.liu@intel.com&gt;
Cc: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
Cc: Geert Uytterhoeven &lt;geert@linux-m68k.org&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Cc: "Peter Zijlstra (Intel)" &lt;peterz@infradead.org&gt;
</content>
</entry>
<entry>
<title>locking/arch: Rename all internal __xchg() names to __arch_xchg()</title>
<updated>2023-04-29T07:08:44Z</updated>
<author>
<name>Andrzej Hajda</name>
<email>andrzej.hajda@intel.com</email>
</author>
<published>2023-01-18T15:44:44Z</published>
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<id>urn:sha1:068550631fbe0b7fb41625cea6fb204fdc8cb224</id>
<content type='text'>
Decrease the probability of this internal facility to be used by
driver code.

Signed-off-by: Andrzej Hajda &lt;andrzej.hajda@intel.com&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
Reviewed-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Reviewed-by: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
Acked-by: Geert Uytterhoeven &lt;geert@linux-m68k.org&gt; [m68k]
Acked-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt; [riscv]
Link: https://lore.kernel.org/r/20230118154450.73842-1-andrzej.hajda@intel.com
Cc: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
</entry>
<entry>
<title>xtensa: use a14 instead of a15 in inline assembly</title>
<updated>2021-10-19T05:19:34Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2021-07-24T06:17:04Z</published>
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<id>urn:sha1:eda8dd1224d6c1c89eb6b687264da9ccfbffb0fd</id>
<content type='text'>
a15 is a frame pointer in the call0 xtensa ABI, don't use it explicitly
in the inline assembly. Use a14 instead, as it has the same properties
as a15 w.r.t. window overflow.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>locking/atomic: xtensa: move to ARCH_ATOMIC</title>
<updated>2021-05-26T11:20:52Z</updated>
<author>
<name>Mark Rutland</name>
<email>mark.rutland@arm.com</email>
</author>
<published>2021-05-25T14:02:30Z</published>
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<id>urn:sha1:b9b12978a8e9a4bb77746e74eae37e587f7f8994</id>
<content type='text'>
We'd like all architectures to convert to ARCH_ATOMIC, as once all
architectures are converted it will be possible to make significant
cleanups to the atomics headers, and this will make it much easier to
generically enable atomic functionality (e.g. debug logic in the
instrumented wrappers).

As a step towards that, this patch migrates xtensa to ARCH_ATOMIC. The
arch code provides arch_{atomic,atomic64,xchg,cmpxchg}*(), and common
code wraps these with optional instrumentation to provide the regular
functions.

Signed-off-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Acked-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
Cc: Boqun Feng &lt;boqun.feng@gmail.com&gt;
Cc: Chris Zankel &lt;chris@zankel.net&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Will Deacon &lt;will@kernel.org&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Link: https://lore.kernel.org/r/20210525140232.53872-32-mark.rutland@arm.com
</content>
</entry>
<entry>
<title>locking/atomic: cmpxchg: make `generic` a prefix</title>
<updated>2021-05-26T11:20:50Z</updated>
<author>
<name>Mark Rutland</name>
<email>mark.rutland@arm.com</email>
</author>
<published>2021-05-25T14:02:10Z</published>
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<id>urn:sha1:6988631bdfddcedc1d27f83723ea36a442f00ea1</id>
<content type='text'>
The asm-generic implementations of cmpxchg_local() and cmpxchg64_local()
use a `_generic` suffix to distinguish themselves from arch code or
wrappers used elsewhere.

Subsequent patches will add ARCH_ATOMIC support to these
implementations, and will distinguish more functions with a `generic`
portion. To align with how ARCH_ATOMIC uses an `arch_` prefix, it would
be helpful to use a `generic_` prefix rather than a `_generic` suffix.

In preparation for this, this patch renames the existing functions to
make `generic` a prefix rather than a suffix. There should be no
functional change as a result of this patch.

Signed-off-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Acked-by: Geert Uytterhoeven &lt;geert@linux-m68k.org&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Cc: Boqun Feng &lt;boqun.feng@gmail.com&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Will Deacon &lt;will@kernel.org&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Link: https://lore.kernel.org/r/20210525140232.53872-12-mark.rutland@arm.com
</content>
</entry>
<entry>
<title>xtensa: use "m" constraint instead of "a" in cmpxchg.h assembly</title>
<updated>2019-11-26T19:33:39Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2019-10-16T07:49:54Z</published>
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<id>urn:sha1:cf3b3baa712517c4972339b150f79fa88099e5db</id>
<content type='text'>
Use "m" constraint instead of "r" for the address, as "m" allows
compiler to access adjacent locations using base + offset, while "r"
requires updating the base register every time.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: use named assembly arguments in cmpxchg.h</title>
<updated>2019-11-26T19:33:39Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2019-10-16T08:52:38Z</published>
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<id>urn:sha1:812e708a4c2d29664a009805671d98cbe7c756b1</id>
<content type='text'>
Numeric assembly arguments are hard to understand and assembly code that
uses them is hard to modify. Use named arguments in __cmpxchg_u32 and
xchg_u32.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: add exclusive atomics support</title>
<updated>2019-05-07T17:36:31Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2018-12-21T01:18:12Z</published>
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<id>urn:sha1:f7c34874f04a80d6c39a32f08da2529e59602d3c</id>
<content type='text'>
Implement atomic primitives using exclusive access opcodes available in
the recent xtensa cores.
Since l32ex/s32ex don't have any memory ordering guarantees don't define
__smp_mb__before_atomic/__smp_mb__after_atomic to make them use memw.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: provide xchg for sizes 1 and 2</title>
<updated>2019-02-07T20:24:17Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2019-01-02T03:29:07Z</published>
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<id>urn:sha1:af3d890b4303cfc9df4b785c852246d4c7013436</id>
<content type='text'>
This is required for generic queued spinlocks, implement it.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
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