x86/boot/compressed/64: Add stage1 #VC handler

2020-09-07T17:45:25Z

Add the first handler for #VC exceptions. At stage 1 there is no GHCB yet because the kernel might still be running on the EFI page table. The stage 1 handler is limited to the MSR-based protocol to talk to the hypervisor and can only support CPUID exit-codes, but that is enough to get to stage 2. [ bp: Zap superfluous newlines after rd/wrmsr instruction mnemonics. ] Signed-off-by: Joerg Roedel Signed-off-by: Borislav Petkov Link: https://lkml.kernel.org/r/20200907131613.12703-20-joro@8bytes.org

x86/traps: Split trap numbers out in a separate header

2020-06-11T13:14:42Z

So they can be used in ASM code. For this it is also necessary to convert them to defines. Will be used for the rework of the entry code. Signed-off-by: Thomas Gleixner Reviewed-by: Andy Lutomirski Reviewed-by: Alexandre Chartre Acked-by: Peter Zijlstra Link: https://lkml.kernel.org/r/20200505134903.731004084@linutronix.de

kernel/arch/x86/include/asm/trapnr.h, branch linux-5.14.y

x86/boot/compressed/64: Add stage1 #VC handler

x86/traps: Split trap numbers out in a separate header