kernel/arch/sh/include/cpu-sh4/cpu/mmu_context.h, branch linux-6.2.y

sh: include: convert to SPDX identifiers

2018-12-28T20:11:45Z

Update license to use SPDX-License-Identifier instead of verbose license text. Link: http://lkml.kernel.org/r/87ftvccszx.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Kuninori Morimoto Reviewed-by: Simon Horman Cc: Rich Felker Cc: Yoshinori Sato Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

sh: Disable MMUCR_AT for SH-4 nommu.

2010-04-07T08:08:32Z

Presently address translation is default-enabled regardless of whether CONFIG_MMU is set or not in the SH-4 case, this fixes it up, and also makes the control init word a bit more readable in the process. Signed-off-by: Paul Mundt

sh: tlb debugfs support.

2010-03-29T06:24:54Z

Export the status of the utlb and itlb entries through debugfs. Signed-off-by: Matt Fleming Signed-off-by: Paul Mundt

sh: update the TLB replacement counter for entry wiring.

2010-03-26T02:37:16Z

Presently the TLB wiring code depends on MMUCR.URB for working out where to place the wired entry, but fails to take the replacment counter in to consideration. This fixes up the wiring logic and ensures that wired entries remain so. Signed-off-by: Matt Fleming Signed-off-by: Paul Mundt

sh: Flush ITLB too in PTEAEX's flush_tlb_page()

2010-03-23T04:36:15Z

flush_tlb_page() can be used to flush TLB entries that map executable pages. Therefore, we need to ensure that the ITLB is also flushed in local_flush_tlb_page(). Signed-off-by: Matt Fleming Signed-off-by: Paul Mundt

sh: New extended page flag to wire/unwire TLB entries

2010-01-16T14:28:57Z

Provide a new extended page flag, _PAGE_WIRED and an SH4 implementation for wiring TLB entries and use it in the fixmap code path so that we can wire the fixmap TLB entry. Signed-off-by: Matt Fleming

sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores.

2009-03-17T08:49:49Z

This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores that implement the PTAEX register and respective functionality. Presently only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs). The main change is in how the PTE is written out when loading the entry in to the TLB, as well as in how the TLB entry is selectively flushed. While SH-X2 extended mode splits out the memory-mapped U and I-TLB data arrays for extra bits, extended ASID mode splits out the address arrays. While we don't use the memory-mapped data array access, the address array accesses are necessary for selective TLB flushes, so these are implemented newly and replace the generic SH-4 implementation. With this, TLB flushes in switch_mm() are almost non-existent on newer parts. Signed-off-by: Paul Mundt

sh: migrate to arch/sh/include/

2008-07-28T23:09:44Z

This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac. Most of the moving about was done with Sam's directions at: http://marc.info/?l=linux-sh&m=121724823706062&w=2 with subsequent hacking and fixups entirely my fault. Signed-off-by: Sam Ravnborg Signed-off-by: Paul Mundt