<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/arch/riscv, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y'/>
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<updated>2019-07-14T06:09:40Z</updated>
<entry>
<title>riscv: Fix udelay in RV32.</title>
<updated>2019-07-14T06:09:40Z</updated>
<author>
<name>Nick Hu</name>
<email>nickhu@andestech.com</email>
</author>
<published>2019-05-30T07:01:17Z</published>
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<id>urn:sha1:82045b8cbcc68e3f8d38e89a0ff48fc99178c2be</id>
<content type='text'>
[ Upstream commit d0e1f2110a5eeb6e410b2dd37d98bc5b30da7bc7 ]

In RV32, udelay would delay the wrong cycle. When it shifts right
"UDELAY_SHIFT" bits, it either delays 0 cycle or 1 cycle. It only works
correctly in RV64. Because the 'ucycles' always needs to be 64 bits
variable.

Signed-off-by: Nick Hu &lt;nickhu@andestech.com&gt;
Reviewed-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
[paul.walmsley@sifive.com: fixed minor spelling error]
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>RISC-V: defconfig: enable clocks, serial console</title>
<updated>2019-07-14T06:09:40Z</updated>
<author>
<name>Kevin Hilman</name>
<email>khilman@baylibre.com</email>
</author>
<published>2019-06-05T17:50:42Z</published>
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<id>urn:sha1:2f9f960af41c8a119a47a19f094d5063bb6e7667</id>
<content type='text'>
[ Upstream commit 3b025f2bc98973f181d926192b0ceb6ced0f86d2 ]

Enable PRCI clock driver and serial console by default, so the default
upstream defconfig is bootable to a serial console.

Signed-off-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>bpf, riscv: clear high 32 bits for ALU32 add/sub/neg/lsh/rsh/arsh</title>
<updated>2019-07-14T06:09:37Z</updated>
<author>
<name>Luke Nelson</name>
<email>luke.r.nels@gmail.com</email>
</author>
<published>2019-05-30T22:29:22Z</published>
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<id>urn:sha1:bb1965c6d7afe5613adc882785a1a183085a26c8</id>
<content type='text'>
[ Upstream commit 1e692f09e091bf5c8b38384f297d6dae5dbf0f12 ]

In BPF, 32-bit ALU operations should zero-extend their results into
the 64-bit registers.

The current BPF JIT on RISC-V emits incorrect instructions that perform
sign extension only (e.g., addw, subw) on 32-bit add, sub, lsh, rsh,
arsh, and neg. This behavior diverges from the interpreter and JITs
for other architectures.

This patch fixes the bugs by performing zero extension on the destination
register of 32-bit ALU operations.

Fixes: 2353ecc6f91f ("bpf, riscv: add BPF JIT for RV64G")
Cc: Xi Wang &lt;xi.wang@gmail.com&gt;
Signed-off-by: Luke Nelson &lt;luke.r.nels@gmail.com&gt;
Acked-by: Song Liu &lt;songliubraving@fb.com&gt;
Acked-by: Björn Töpel &lt;bjorn.topel@gmail.com&gt;
Reviewed-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Signed-off-by: Alexei Starovoitov &lt;ast@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>bpf, riscv: clear target register high 32-bits for and/or/xor on ALU32</title>
<updated>2019-07-14T06:09:35Z</updated>
<author>
<name>Björn Töpel</name>
<email>bjorn.topel@gmail.com</email>
</author>
<published>2019-05-21T13:46:22Z</published>
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<id>urn:sha1:a1dbf72838b0f889d9c846076235eee527372d8f</id>
<content type='text'>
[ Upstream commit fe121ee531d1362810bfd30f38a1b88b1d3d376c ]

When using 32-bit subregisters (ALU32), the RISC-V JIT would not clear
the high 32-bits of the target register and therefore generate
incorrect code.

E.g., in the following code:

  $ cat test.c
  unsigned int f(unsigned long long a,
  	       unsigned int b)
  {
  	return (unsigned int)a &amp; b;
  }

  $ clang-9 -target bpf -O2 -emit-llvm -S test.c -o - | \
  	llc-9 -mattr=+alu32 -mcpu=v3
  	.text
  	.file	"test.c"
  	.globl	f
  	.p2align	3
  	.type	f,@function
  f:
  	r0 = r1
  	w0 &amp;= w2
  	exit
  .Lfunc_end0:
  	.size	f, .Lfunc_end0-f

The JIT would not clear the high 32-bits of r0 after the
and-operation, which in this case might give an incorrect return
value.

After this patch, that is not the case, and the upper 32-bits are
cleared.

Reported-by: Jiong Wang &lt;jiong.wang@netronome.com&gt;
Fixes: 2353ecc6f91f ("bpf, riscv: add BPF JIT for RV64G")
Signed-off-by: Björn Töpel &lt;bjorn.topel@gmail.com&gt;
Signed-off-by: Daniel Borkmann &lt;daniel@iogearbox.net&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>riscv: mm: synchronize MMU after pte change</title>
<updated>2019-06-25T03:34:53Z</updated>
<author>
<name>ShihPo Hung</name>
<email>shihpo.hung@sifive.com</email>
</author>
<published>2019-06-17T04:26:17Z</published>
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<id>urn:sha1:1243385929aec703ff57ad0bc1eed3fead3a351d</id>
<content type='text'>
commit bf587caae305ae3b4393077fb22c98478ee55755 upstream.

Because RISC-V compliant implementations can cache invalid entries
in TLB, an SFENCE.VMA is necessary after changes to the page table.
This patch adds an SFENCE.vma for the vmalloc_fault path.

Signed-off-by: ShihPo Hung &lt;shihpo.hung@sifive.com&gt;
[paul.walmsley@sifive.com: reversed tab-&gt;whitespace conversion,
 wrapped comment lines]
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
Cc: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Cc: Albert Ou &lt;aou@eecs.berkeley.edu&gt;
Cc: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
Cc: linux-riscv@lists.infradead.org
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systems</title>
<updated>2019-04-10T16:41:40Z</updated>
<author>
<name>Anup Patel</name>
<email>Anup.Patel@wdc.com</email>
</author>
<published>2019-04-05T05:49:34Z</published>
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<id>urn:sha1:f05badde4e20d2e0f8c39d07a6873b2bfb0754f8</id>
<content type='text'>
The Maximum Physical Memory 2GiB option for 64bit systems is currently
broken because kernel hangs at boot-time when this option is enabled
and the underlying system has more than 2GiB memory.

This issue can be easily reproduced on SiFive Unleashed board where
we have 8GiB of memory.

This patch fixes above issue by removing unusable memory region in
setup_bootmem().

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: Add separate defconfig for 32bit systems</title>
<updated>2019-04-09T16:42:49Z</updated>
<author>
<name>Anup Patel</name>
<email>Anup.Patel@wdc.com</email>
</author>
<published>2019-03-12T22:08:12Z</published>
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<id>urn:sha1:1b937e8faa87ccfb4b7d5b230796fa67bc8a183b</id>
<content type='text'>
This patch adds rv32_defconfig for 32bit systems. The only
difference between rv32_defconfig and defconfig is that
rv32_defconfig has  CONFIG_ARCH_RV32I=y.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'trace-5.1-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace</title>
<updated>2019-04-05T23:15:57Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2019-04-05T23:15:57Z</published>
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<id>urn:sha1:970b766cfd3f3cb7275bf51144b1678c547882fc</id>
<content type='text'>
Pull syscall-get-arguments cleanup and fixes from Steven Rostedt:
 "Andy Lutomirski approached me to tell me that the
  syscall_get_arguments() implementation in x86 was horrible and gcc
  certainly gets it wrong.

  He said that since the tracepoints only pass in 0 and 6 for i and n
  repectively, it should be optimized for that case. Inspecting the
  kernel, I discovered that all users pass in 0 for i and only one file
  passing in something other than 6 for the number of arguments. That
  code happens to be my own code used for the special syscall tracing.

  That can easily be converted to just using 0 and 6 as well, and only
  copying what is needed. Which is probably the faster path anyway for
  that case.

  Along the way, a couple of real fixes came from this as the
  syscall_get_arguments() function was incorrect for csky and riscv.

  x86 has been optimized to for the new interface that removes the
  variable number of arguments, but the other architectures could still
  use some loving and take more advantage of the simpler interface"

* tag 'trace-5.1-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace:
  syscalls: Remove start and number from syscall_set_arguments() args
  syscalls: Remove start and number from syscall_get_arguments() args
  csky: Fix syscall_get_arguments() and syscall_set_arguments()
  riscv: Fix syscall_get_arguments() and syscall_set_arguments()
  tracing/syscalls: Pass in hardcoded 6 into syscall_get_arguments()
  ptrace: Remove maxargs from task_current_syscall()
</content>
</entry>
<entry>
<title>syscalls: Remove start and number from syscall_set_arguments() args</title>
<updated>2019-04-05T13:27:23Z</updated>
<author>
<name>Steven Rostedt (VMware)</name>
<email>rostedt@goodmis.org</email>
</author>
<published>2019-03-28T00:07:31Z</published>
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<id>urn:sha1:32d92586629a8b3637a3c9361709818e25f327ad</id>
<content type='text'>
After removing the start and count arguments of syscall_get_arguments() it
seems reasonable to remove them from syscall_set_arguments(). Note, as of
today, there are no users of syscall_set_arguments(). But we are told that
there will be soon. But for now, at least make it consistent with
syscall_get_arguments().

Link: http://lkml.kernel.org/r/20190327222014.GA32540@altlinux.org

Cc: Oleg Nesterov &lt;oleg@redhat.com&gt;
Cc: Kees Cook &lt;keescook@chromium.org&gt;
Cc: Andy Lutomirski &lt;luto@amacapital.net&gt;
Cc: Dominik Brodowski &lt;linux@dominikbrodowski.net&gt;
Cc: Dave Martin &lt;dave.martin@arm.com&gt;
Cc: "Dmitry V. Levin" &lt;ldv@altlinux.org&gt;
Cc: x86@kernel.org
Cc: linux-snps-arc@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-c6x-dev@linux-c6x.org
Cc: uclinux-h8-devel@lists.sourceforge.jp
Cc: linux-hexagon@vger.kernel.org
Cc: linux-ia64@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: nios2-dev@lists.rocketboards.org
Cc: openrisc@lists.librecores.org
Cc: linux-parisc@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-s390@vger.kernel.org
Cc: linux-sh@vger.kernel.org
Cc: sparclinux@vger.kernel.org
Cc: linux-um@lists.infradead.org
Cc: linux-xtensa@linux-xtensa.org
Cc: linux-arch@vger.kernel.org
Acked-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt; # For xtensa changes
Acked-by: Will Deacon &lt;will.deacon@arm.com&gt; # For the arm64 bits
Reviewed-by: Thomas Gleixner &lt;tglx@linutronix.de&gt; # for x86
Reviewed-by: Dmitry V. Levin &lt;ldv@altlinux.org&gt;
Signed-off-by: Steven Rostedt (VMware) &lt;rostedt@goodmis.org&gt;
</content>
</entry>
<entry>
<title>syscalls: Remove start and number from syscall_get_arguments() args</title>
<updated>2019-04-05T13:26:43Z</updated>
<author>
<name>Steven Rostedt (Red Hat)</name>
<email>rostedt@goodmis.org</email>
</author>
<published>2016-11-07T21:26:37Z</published>
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<id>urn:sha1:b35f549df1d7520d37ba1e6d4a8d4df6bd52d136</id>
<content type='text'>
At Linux Plumbers, Andy Lutomirski approached me and pointed out that the
function call syscall_get_arguments() implemented in x86 was horribly
written and not optimized for the standard case of passing in 0 and 6 for
the starting index and the number of system calls to get. When looking at
all the users of this function, I discovered that all instances pass in only
0 and 6 for these arguments. Instead of having this function handle
different cases that are never used, simply rewrite it to return the first 6
arguments of a system call.

This should help out the performance of tracing system calls by ptrace,
ftrace and perf.

Link: http://lkml.kernel.org/r/20161107213233.754809394@goodmis.org

Cc: Oleg Nesterov &lt;oleg@redhat.com&gt;
Cc: Kees Cook &lt;keescook@chromium.org&gt;
Cc: Andy Lutomirski &lt;luto@amacapital.net&gt;
Cc: Dominik Brodowski &lt;linux@dominikbrodowski.net&gt;
Cc: Dave Martin &lt;dave.martin@arm.com&gt;
Cc: "Dmitry V. Levin" &lt;ldv@altlinux.org&gt;
Cc: x86@kernel.org
Cc: linux-snps-arc@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-c6x-dev@linux-c6x.org
Cc: uclinux-h8-devel@lists.sourceforge.jp
Cc: linux-hexagon@vger.kernel.org
Cc: linux-ia64@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: nios2-dev@lists.rocketboards.org
Cc: openrisc@lists.librecores.org
Cc: linux-parisc@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-s390@vger.kernel.org
Cc: linux-sh@vger.kernel.org
Cc: sparclinux@vger.kernel.org
Cc: linux-um@lists.infradead.org
Cc: linux-xtensa@linux-xtensa.org
Cc: linux-arch@vger.kernel.org
Acked-by: Paul Burton &lt;paul.burton@mips.com&gt; # MIPS parts
Acked-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt; # For xtensa changes
Acked-by: Will Deacon &lt;will.deacon@arm.com&gt; # For the arm64 bits
Reviewed-by: Thomas Gleixner &lt;tglx@linutronix.de&gt; # for x86
Reviewed-by: Dmitry V. Levin &lt;ldv@altlinux.org&gt;
Reported-by: Andy Lutomirski &lt;luto@amacapital.net&gt;
Signed-off-by: Steven Rostedt (VMware) &lt;rostedt@goodmis.org&gt;
</content>
</entry>
</feed>
