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<title>kernel/arch/riscv/lib/delay.c, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
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<updated>2019-07-14T06:09:40Z</updated>
<entry>
<title>riscv: Fix udelay in RV32.</title>
<updated>2019-07-14T06:09:40Z</updated>
<author>
<name>Nick Hu</name>
<email>nickhu@andestech.com</email>
</author>
<published>2019-05-30T07:01:17Z</published>
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<id>urn:sha1:82045b8cbcc68e3f8d38e89a0ff48fc99178c2be</id>
<content type='text'>
[ Upstream commit d0e1f2110a5eeb6e410b2dd37d98bc5b30da7bc7 ]

In RV32, udelay would delay the wrong cycle. When it shifts right
"UDELAY_SHIFT" bits, it either delays 0 cycle or 1 cycle. It only works
correctly in RV64. Because the 'ucycles' always needs to be 64 bits
variable.

Signed-off-by: Nick Hu &lt;nickhu@andestech.com&gt;
Reviewed-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
[paul.walmsley@sifive.com: fixed minor spelling error]
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>RISC-V: Export some expected symbols for modules</title>
<updated>2017-11-30T18:01:10Z</updated>
<author>
<name>Olof Johansson</name>
<email>olof@lixom.net</email>
</author>
<published>2017-11-30T01:55:16Z</published>
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<content type='text'>
These are the ones needed by current allmodconfig, so add them instead
of everything other architectures are exporting -- the rest can be
added on demand later if needed.

Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: Device, timer, IRQs, and the SBI</title>
<updated>2017-09-26T22:26:47Z</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmer@dabbelt.com</email>
</author>
<published>2017-07-11T01:05:09Z</published>
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<id>urn:sha1:6d60b6ee0c9777b92c47f6dc8aad1dd90612e4fa</id>
<content type='text'>
This patch contains code that interfaces with devices that are mandated
by the RISC-V supervisor specification and that don't have explicit
drivers anywhere else in the tree.  This includes the staticly defined
interrupts, the CSR-mapped timer, and virtualized SBI devices.

Signed-off-by: Palmer Dabbelt &lt;palmer@dabbelt.com&gt;
</content>
</entry>
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