<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/arch/riscv/include/uapi/asm/hwprobe.h, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable'/>
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<updated>2025-12-19T07:22:30Z</updated>
<entry>
<title>riscv: hwprobe: export Zilsd and Zclsd ISA extensions</title>
<updated>2025-12-19T07:22:30Z</updated>
<author>
<name>Pincheng Wang</name>
<email>pincheng.plct@isrc.iscas.ac.cn</email>
</author>
<published>2025-08-26T16:29:37Z</published>
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<id>urn:sha1:6118ebed3bdf896038f58d0d1804f551f33e8643</id>
<content type='text'>
Export Zilsd and Zclsd ISA extensions through hwprobe.

Signed-off-by: Pincheng Wang &lt;pincheng.plct@isrc.iscas.ac.cn&gt;
Reviewed-by: Nutty Liu &lt;nutty.liu@hotmail.com&gt;
Link: https://patch.msgid.link/20250826162939.1494021-4-pincheng.plct@isrc.iscas.ac.cn
[pjw@kernel.org: fixed whitespace; updated to apply]
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;</content>
</entry>
<entry>
<title>riscv: hwprobe: Expose Zicbop extension and its block size</title>
<updated>2025-11-19T16:19:29Z</updated>
<author>
<name>Yao Zihong</name>
<email>zihong.plct@isrc.iscas.ac.cn</email>
</author>
<published>2025-11-18T16:23:24Z</published>
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<id>urn:sha1:e0a504984a88a2f1c0131aca5115fd529fc9974a</id>
<content type='text'>
- Add `RISCV_HWPROBE_EXT_ZICBOP` to report the presence of the
  Zicbop extension.
- Add `RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE` to expose the block
  size (in bytes) when Zicbop is supported.
- Update hwprobe.rst to document the new extension bit and block
  size key, following the existing Zicbom/Zicboz style.

Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Yao Zihong &lt;zihong.plct@isrc.iscas.ac.cn&gt;
Link: https://patch.msgid.link/20251118162436.15485-2-zihong.plct@isrc.iscas.ac.cn
[pjw@kernel.org: updated to apply]
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;</content>
</entry>
<entry>
<title>riscv: hwprobe: Export Zalasr extension</title>
<updated>2025-11-19T16:19:28Z</updated>
<author>
<name>Xu Lu</name>
<email>luxu.kernel@bytedance.com</email>
</author>
<published>2025-10-20T04:20:49Z</published>
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<id>urn:sha1:f4922b69165735e81752ee47d174f873e989a449</id>
<content type='text'>
Export the Zalasr extension to userspace using hwprobe.

Signed-off-by: Xu Lu &lt;luxu.kernel@bytedance.com&gt;
Link: https://patch.msgid.link/20251020042056.30283-4-luxu.kernel@bytedance.com
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;</content>
</entry>
<entry>
<title>riscv: hwprobe: Add MIPS vendor extension probing</title>
<updated>2025-09-19T16:33:56Z</updated>
<author>
<name>Aleksa Paunovic</name>
<email>aleksa.paunovic@htecgroup.com</email>
</author>
<published>2025-07-24T15:23:28Z</published>
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<id>urn:sha1:bb4b0f8a1bcbf8f4e3a0841aaefb3fd580d12fc9</id>
<content type='text'>
Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0" which allows
userspace to probe for the new xmipsexectl vendor extension.

Signed-off-by: Aleksa Paunovic &lt;aleksa.paunovic@htecgroup.com&gt;
Reviewed-by: Alexandre Ghiti &lt;alexghiti@rivosinc.com&gt;
Link: https://lore.kernel.org/r/20250724-p8700-pause-v5-4-a6cbbe1c3412@htecgroup.com
[pjw@kernel.org: fixed some checkpatch issues]
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;</content>
</entry>
<entry>
<title>Merge tag 'riscv-mw1-6.16-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux into for-next</title>
<updated>2025-06-05T19:26:06Z</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmer@dabbelt.com</email>
</author>
<published>2025-06-05T18:11:21Z</published>
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<id>urn:sha1:9d3da7827536b8e41e4188185622816a105b46f7</id>
<content type='text'>
riscv patches for 6.16-rc1

* Implement atomic patching support for ftrace which finally allows to
  get rid of stop_machine().
* Support for kexec_file_load() syscall
* Improve module loading time by changing the algorithm that counts the
  number of plt/got entries in a module.
* Zicbop is now used in the kernel to prefetch instructions

[Palmer: There's been two rounds of surgery on this one, so as a result
it's a bit different than the PR.]

* alex-pr: (734 commits)
  riscv: Improve Kconfig help for RISCV_ISA_V_PREEMPTIVE
  MAINTAINERS: Update Atish's email address
  riscv: hwprobe: export Zabha extension
  riscv: Make regs_irqs_disabled() more clear
  perf symbols: Ignore mapping symbols on riscv
  RISC-V: Kconfig: Fix help text of CMDLINE_EXTEND
  riscv: module: Optimize PLT/GOT entry counting
  riscv: Add support for PUD THP
  riscv: xchg: Prefetch the destination word for sc.w
  riscv: Add ARCH_HAS_PREFETCH[W] support with Zicbop
  riscv: Add support for Zicbop
  riscv: Introduce Zicbop instructions
  riscv/kexec_file: Fix comment in purgatory relocator
  riscv: kexec_file: Support loading Image binary file
  riscv: kexec_file: Split the loading of kernel and others
  riscv: Documentation: add a description about dynamic ftrace
  riscv: ftrace: support direct call using call_ops
  riscv: Implement HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS
  riscv: ftrace: support PREEMPT
  riscv: add a data fence for CMODX in the kernel mode
  ...

Signed-off-by: Palmer Dabbelt &lt;palmer@dabbelt.com&gt;
</content>
</entry>
<entry>
<title>riscv: hwprobe: export Zabha extension</title>
<updated>2025-06-05T18:10:18Z</updated>
<author>
<name>Alexandre Ghiti</name>
<email>alexghiti@rivosinc.com</email>
</author>
<published>2025-04-21T14:14:13Z</published>
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<id>urn:sha1:415a8c81da3dab0a585bd4f8d505a11ad5a171a7</id>
<content type='text'>
Export Zabha through the hwprobe syscall.

Reviewed-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Link: https://lore.kernel.org/r/20250421141413.394444-1-alexghiti@rivosinc.com
Signed-off-by: Alexandre Ghiti &lt;alexghiti@rivosinc.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@dabbelt.com&gt;
</content>
</entry>
<entry>
<title>riscv: hwprobe: Document SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions</title>
<updated>2025-05-08T18:01:43Z</updated>
<author>
<name>Cyan Yang</name>
<email>cyan.yang@sifive.com</email>
</author>
<published>2025-04-18T05:32:30Z</published>
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<id>urn:sha1:e8fd215ed0eb814486d50b4835007cbc50b2c2b7</id>
<content type='text'>
Document the support for sifive vendor extensions using the key
RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0 and two vendor extensions for SiFive
Int8 Matrix Multiplication Instructions using
RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD and
RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ.

Signed-off-by: Cyan Yang &lt;cyan.yang@sifive.com&gt;
Link: https://lore.kernel.org/r/20250418053239.4351-4-cyan.yang@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>riscv: hwprobe: export Zaamo and Zalrsc extensions</title>
<updated>2025-03-19T12:03:45Z</updated>
<author>
<name>Clément Léger</name>
<email>cleger@rivosinc.com</email>
</author>
<published>2024-06-19T15:39:10Z</published>
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<id>urn:sha1:9d45d1ff90a6888f6138eb7e1f2619ef427831d3</id>
<content type='text'>
Export the Zaamo and Zalrsc extensions to userspace using hwprobe.

Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reviewed-by: Charlie Jenkins &lt;charlie@rivosinc.com&gt;
Link: https://lore.kernel.org/r/20240619153913.867263-4-cleger@rivosinc.com
Signed-off-by: Alexandre Ghiti &lt;alexghiti@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: hwprobe: Expose Zicbom extension and its block size</title>
<updated>2025-03-18T12:43:56Z</updated>
<author>
<name>Yunhui Cui</name>
<email>cuiyunhui@bytedance.com</email>
</author>
<published>2025-02-26T06:32:05Z</published>
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<id>urn:sha1:eb10039709402cc1fab1533a1ecc1a54c2152e68</id>
<content type='text'>
Expose Zicbom through hwprobe and also provide a key to extract its
respective block size.

[ alex: Fix merge conflicts and hwprobe numbering ]

Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Signed-off-by: Yunhui Cui &lt;cuiyunhui@bytedance.com&gt;
Link: https://lore.kernel.org/r/20250226063206.71216-3-cuiyunhui@bytedance.com
Signed-off-by: Alexandre Ghiti &lt;alexghiti@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>Merge patch series "riscv: Add bfloat16 instruction support"</title>
<updated>2025-03-18T11:52:54Z</updated>
<author>
<name>Alexandre Ghiti</name>
<email>alexghiti@rivosinc.com</email>
</author>
<published>2025-03-18T11:52:54Z</published>
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<id>urn:sha1:2f2cd9f33435834a6dfca406bb121ff9a885fb23</id>
<content type='text'>
Inochi Amaoto &lt;inochiama@gmail.com&gt; says:

Add description for the BFloat16 precision Floating-Point ISA extension,
(Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62
("Added Chapter title to BF16") of the riscv-isa-manual.

* patches from https://lore.kernel.org/r/20250213003849.147358-1-inochiama@gmail.com:
  riscv: hwprobe: export bfloat16 ISA extension
  riscv: add ISA extension parsing for bfloat16 ISA extension
  dt-bindings: riscv: add bfloat16 ISA extension description

Signed-off-by: Alexandre Ghiti &lt;alexghiti@rivosinc.com&gt;
Link: https://lore.kernel.org/r/20250213003849.147358-1-inochiama@gmail.com
</content>
</entry>
</feed>
