kernel/arch/riscv/include/uapi/asm/elf.h, branch linux-rolling-stable

riscv: Add remaining module relocations

2023-11-07T22:59:31Z

Add all final module relocations and add error logs explaining the ones that are not supported. Implement overflow checks for ADD/SUB/SET/ULEB128 relocations. Signed-off-by: Charlie Jenkins Link: https://lore.kernel.org/r/20231101-module_relocations-v9-2-8dfa3483c400@rivosinc.com Signed-off-by: Palmer Dabbelt

riscv: clean up the macro format in each header file

2019-11-12T20:04:52Z

There are many different formats in each header now, such as _ASM_XXX_H, __ASM_XXX_H, _ASM_RISCV_XXX_H, RISCV_XXX_H, etc., This patch tries to unify the format by using _ASM_RISCV_XXX_H, because the most header use it now. This patch also adds the conditional to the headers if they lost it. Signed-off-by: Zong Li Signed-off-by: Paul Walmsley

RISC-V: Add FP register ptrace support for gdb.

2018-10-23T00:38:04Z

Add a variable and a macro to describe FP registers, assuming only D is supported. FP code is conditional on CONFIG_FPU. The FP regs and FCSR are copied separately to avoid copying struct padding. Tested by hand and with the gdb testsuite. Signed-off-by: Jim Wilson Signed-off-by: Palmer Dabbelt

RISC-V: Add definiion of extract symbol's index and type for 32-bit

2018-07-04T20:54:08Z

Use generic marco to get the index and type of symbol. Signed-off-by: Zong Li Signed-off-by: Palmer Dabbelt

RISC-V: Add definition of relocation types

2018-04-03T03:00:56Z

Signed-off-by: Zong Li Signed-off-by: Palmer Dabbelt

RISC-V: User-facing API

2017-09-26T22:26:48Z

This patch contains code that is in some way visible to the user: including via system calls, the VDSO, module loading and signal handling. It also contains some generic code that is ABI visible. Signed-off-by: Palmer Dabbelt