<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/arch/riscv/include/asm/vdso, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
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<updated>2025-10-18T04:23:11Z</updated>
<entry>
<title>riscv: hwprobe: Fix stale vDSO data for late-initialized keys at boot</title>
<updated>2025-10-18T04:23:11Z</updated>
<author>
<name>Jingwei Wang</name>
<email>wangjingwei@iscas.ac.cn</email>
</author>
<published>2025-08-11T14:20:06Z</published>
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<id>urn:sha1:5d15d2ad36b0f7afab83ca9fc8a2a6e60cbe54c4</id>
<content type='text'>
The hwprobe vDSO data for some keys, like MISALIGNED_VECTOR_PERF,
is determined by an asynchronous kthread. This can create a race
condition where the kthread finishes after the vDSO data has
already been populated, causing userspace to read stale values.

To fix this race, a new 'ready' flag is added to the vDSO data,
initialized to 'false' during arch_initcall_sync. This flag is
checked by both the vDSO's user-space code and the riscv_hwprobe
syscall. The syscall serves as a one-time gate, using a completion
to wait for any pending probes before populating the data and
setting the flag to 'true', thus ensuring userspace reads fresh
values on its first request.

Reported-by: Tsukasa OI &lt;research_trasio@irq.a4lg.com&gt;
Closes: https://lore.kernel.org/linux-riscv/760d637b-b13b-4518-b6bf-883d55d44e7f@irq.a4lg.com/
Fixes: e7c9d66e313b ("RISC-V: Report vector unaligned access speed hwprobe")
Cc: Palmer Dabbelt &lt;palmer@dabbelt.com&gt;
Cc: Alexandre Ghiti &lt;alexghiti@rivosinc.com&gt;
Cc: Olof Johansson &lt;olof@lixom.net&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Alexandre Ghiti &lt;alexghiti@rivosinc.com&gt;
Co-developed-by: Palmer Dabbelt &lt;palmer@dabbelt.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@dabbelt.com&gt;
Signed-off-by: Jingwei Wang &lt;wangjingwei@iscas.ac.cn&gt;
Link: https://lore.kernel.org/r/20250811142035.105820-1-wangjingwei@iscas.ac.cn
[pjw@kernel.org: fix checkpatch issues]
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;</content>
</entry>
<entry>
<title>riscv: errata: Fix the PAUSE Opcode for MIPS P8700</title>
<updated>2025-09-19T16:33:56Z</updated>
<author>
<name>Djordje Todorovic</name>
<email>djordje.todorovic@htecgroup.com</email>
</author>
<published>2025-07-24T15:23:31Z</published>
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<id>urn:sha1:0b0ca959d20689fece038954bbf1d7b14c0b11c3</id>
<content type='text'>
Add ERRATA_MIPS and ERRATA_MIPS_P8700_PAUSE_OPCODE configs.
Handle errata for the MIPS PAUSE instruction.

Signed-off-by: Djordje Todorovic &lt;djordje.todorovic@htecgroup.com&gt;
Signed-off-by: Aleksandar Rikalo &lt;arikalo@gmail.com&gt;
Signed-off-by: Raj Vishwanathan4 &lt;rvishwanathan@mips.com&gt;
Signed-off-by: Aleksa Paunovic &lt;aleksa.paunovic@htecgroup.com&gt;
Reviewed-by: Alexandre Ghiti &lt;alexghiti@rivosinc.com&gt;
Link: https://lore.kernel.org/r/20250724-p8700-pause-v5-7-a6cbbe1c3412@htecgroup.com
[pjw@kernel.org: updated to apply and compile; fixed a checkpatch issue]
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;</content>
</entry>
<entry>
<title>riscv: Replace __ASSEMBLY__ with __ASSEMBLER__ in non-uapi headers</title>
<updated>2025-09-16T22:25:30Z</updated>
<author>
<name>Thomas Huth</name>
<email>thuth@redhat.com</email>
</author>
<published>2025-06-06T07:09:52Z</published>
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<id>urn:sha1:f811f58597acba9100dd61cdef052d1d1f931968</id>
<content type='text'>
While the GCC and Clang compilers already define __ASSEMBLER__
automatically when compiling assembly code, __ASSEMBLY__ is a
macro that only gets defined by the Makefiles in the kernel.
This can be very confusing when switching between userspace
and kernelspace coding, or when dealing with uapi headers that
rather should use __ASSEMBLER__ instead. So let's standardize on
the __ASSEMBLER__ macro that is provided by the compilers now.

This originally was a completely mechanical patch (done with a
simple "sed -i" statement), with some manual fixups during
rebasing of the patch later.

Cc: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
Cc: Palmer Dabbelt &lt;palmer@dabbelt.com&gt;
Cc: Albert Ou &lt;aou@eecs.berkeley.edu&gt;
Cc: Alexandre Ghiti &lt;alex@ghiti.fr&gt;
Cc: linux-riscv@lists.infradead.org
Signed-off-by: Thomas Huth &lt;thuth@redhat.com&gt;
Link: https://lore.kernel.org/r/20250606070952.498274-3-thuth@redhat.com
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;</content>
</entry>
<entry>
<title>RISC-V: vDSO: Correct inline assembly constraints in the getrandom syscall wrapper</title>
<updated>2025-06-12T19:13:57Z</updated>
<author>
<name>Xi Ruoyao</name>
<email>xry111@xry111.site</email>
</author>
<published>2025-06-06T09:24:44Z</published>
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<id>urn:sha1:2b9518684f8558cd61a7c608cc03a27822cf7b03</id>
<content type='text'>
As recently pointed out by Thomas, if a register is forced for two
different register variables, among them one is used as "+" (both input
and output) and another is only used as input, Clang would treat the
conflicting input parameters as undefined behaviour and optimize away
the argument assignment.

Instead use "=r" (only output) for the output parameter and "r" (only
input) for the input parameter.
While the example from the GCC documentation uses "0" for the input
parameter, this is not necessary as confirmed by the GCC developers and "r"
matches what the other architectures' vDSO implementations are using.

[ alex: Update log to match v2 (Thomas) ]

Link: https://lore.kernel.org/all/20250603-loongarch-vdso-syscall-v1-1-6d12d6dfbdd0@linutronix.de/
Link: https://gcc.gnu.org/onlinedocs/gcc-15.1.0/gcc/Local-Register-Variables.html
Link: https://gcc.gnu.org/pipermail/gcc-help/2025-June/144266.html
Cc: Thomas Weißschuh &lt;thomas.weissschuh@linutronix.de&gt;
Cc: Nathan Chancellor &lt;nathan@kernel.org&gt;
Signed-off-by: Xi Ruoyao &lt;xry111@xry111.site&gt;
Reviewed-by: Thomas Weißschuh &lt;thomas.weissschuh@linutronix.de&gt;
Fixes: ee0d03053e70 ("RISC-V: vDSO: Wire up getrandom() vDSO")
Link: https://lore.kernel.org/r/20250606092443.73650-2-xry111@xry111.site
Signed-off-by: Alexandre Ghiti &lt;alexghiti@rivosinc.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@dabbelt.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: vDSO: Wire up getrandom() vDSO implementation</title>
<updated>2025-06-05T21:03:09Z</updated>
<author>
<name>Xi Ruoyao</name>
<email>xry111@xry111.site</email>
</author>
<published>2025-04-11T02:46:00Z</published>
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<id>urn:sha1:ee0d03053e7009a3a3532fb37f6c94bfa0a8cca3</id>
<content type='text'>
Hook up the generic vDSO implementation to the generic vDSO getrandom
implementation by providing the required __arch_chacha20_blocks_nostack
and getrandom_syscall implementations. Also wire up the selftests.

The benchmark result:

	vdso: 25000000 times in 2.466341333 seconds
	libc: 25000000 times in 41.447720005 seconds
	syscall: 25000000 times in 41.043926672 seconds

	vdso: 25000000 x 256 times in 162.286219353 seconds
	libc: 25000000 x 256 times in 2953.855018685 seconds
	syscall: 25000000 x 256 times in 2796.268546000 seconds

[ alex: - Fix dynamic relocation
        - Squash Nathan's fix https://lore.kernel.org/all/20250423-riscv-fix-compat_vdso-lld-v2-1-b7bbbc244501@kernel.org/
	- Add comment from Loongarch ]

Signed-off-by: Xi Ruoyao &lt;xry111@xry111.site&gt;
Link: https://lore.kernel.org/r/20250411024600.16045-1-xry111@xry111.site
Tested-by: Alexandre Ghiti &lt;alexghiti@rivosinc.com&gt;
Signed-off-by: Alexandre Ghiti &lt;alexghiti@rivosinc.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@dabbelt.com&gt;
</content>
</entry>
<entry>
<title>riscv: vdso: Switch to generic storage implementation</title>
<updated>2025-02-21T08:54:02Z</updated>
<author>
<name>Thomas Weißschuh</name>
<email>thomas.weissschuh@linutronix.de</email>
</author>
<published>2025-02-04T12:05:41Z</published>
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<id>urn:sha1:46fe55b204bfb007e0f0a5409dcda063ad98b089</id>
<content type='text'>
The generic storage implementation provides the same features as the
custom one. However it can be shared between architectures, making
maintenance easier.

Co-developed-by: Nam Cao &lt;namcao@linutronix.de&gt;
Signed-off-by: Nam Cao &lt;namcao@linutronix.de&gt;
Signed-off-by: Thomas Weißschuh &lt;thomas.weissschuh@linutronix.de&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Link: https://lore.kernel.org/all/20250204-vdso-store-rng-v3-9-13a4669dfc8c@linutronix.de

</content>
</entry>
<entry>
<title>vdso: Rename struct arch_vdso_data to arch_vdso_time_data</title>
<updated>2024-11-02T11:37:36Z</updated>
<author>
<name>Nam Cao</name>
<email>namcao@linutronix.de</email>
</author>
<published>2024-10-10T07:01:30Z</published>
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<id>urn:sha1:a812eee0b68645e2916d4a4399280fe5471cac67</id>
<content type='text'>
The struct arch_vdso_data is only about vdso time data. So rename it to
arch_vdso_time_data to make it obvious.
Non time-related data will be migrated out of these structs soon.

Signed-off-by: Nam Cao &lt;namcao@linutronix.de&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Acked-by: Heiko Carstens &lt;hca@linux.ibm.com&gt; # s390
Link: https://lore.kernel.org/all/20241010-vdso-generic-base-v1-28-b64f0842d512@linutronix.de

</content>
</entry>
<entry>
<title>riscv: vdso: Remove timekeeper include</title>
<updated>2024-10-15T15:50:29Z</updated>
<author>
<name>Thomas Weißschuh</name>
<email>thomas.weissschuh@linutronix.de</email>
</author>
<published>2024-10-10T15:44:48Z</published>
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<id>urn:sha1:930916d85a0958827d5150bb506044424adadf21</id>
<content type='text'>
Since the generic VDSO clock mode storage is used, this header file is
unused and can be removed.

This avoids including a non-VDSO header while building the VDSO,
which can lead to compilation errors.

Also drop the comment which is out of date and in the wrong place.

Signed-off-by: Thomas Weißschuh &lt;thomas.weissschuh@linutronix.de&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Link: https://lore.kernel.org/all/20241010-vdso-generic-arch_update_vsyscall-v1-5-7fe5a3ea4382@linutronix.de

</content>
</entry>
<entry>
<title>riscv: Provide a definition for 'pause'</title>
<updated>2024-07-12T10:16:39Z</updated>
<author>
<name>Andrew Jones</name>
<email>ajones@ventanamicro.com</email>
</author>
<published>2024-04-26T10:08:21Z</published>
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<id>urn:sha1:6da111574baffb3399a6bd03a98b269eac9713f2</id>
<content type='text'>
If we're going to provide the encoding for 'pause' in cpu_relax()
anyway, then we can drop the toolchain checks and just always use
it. The advantage of doing this is that other code that need
pause don't need to also define it (yes, another use is coming).
Add the definition to insn-def.h since it's an instruction
definition and also because insn-def.h doesn't include much, so
it's safe to include from asm/vdso/processor.h without concern for
circular dependencies.

Signed-off-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/20240426100820.14762-9-ajones@ventanamicro.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace zihintpause</title>
<updated>2023-11-01T02:15:54Z</updated>
<author>
<name>Minda Chen</name>
<email>minda.chen@starfivetech.com</email>
</author>
<published>2023-08-02T06:42:15Z</published>
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<id>urn:sha1:dd16ac404a685cce07e67261a94c6225d90ea7ba</id>
<content type='text'>
Actually it is a part of Conor's
commit aae538cd03bc ("riscv: fix detection of toolchain
Zihintpause support").
It is looks like a merge issue. Samuel's
commit 0b1d60d6dd9e ("riscv: Fix build with
CONFIG_CC_OPTIMIZE_FOR_SIZE=y") do not base on Conor's commit and
revert to __riscv_zihintpause. So this patch can fix it.

Signed-off-by: Minda Chen &lt;minda.chen@starfivetech.com&gt;
Fixes: 3c349eacc559 ("Merge patch "riscv: Fix build with CONFIG_CC_OPTIMIZE_FOR_SIZE=y"")
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/r/20230802064215.31111-1-minda.chen@starfivetech.com
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
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