kernel/arch/riscv/include/asm/futex.h, branch linux-rolling-stable

riscv/futex: sign extend compare value in atomic cmpxchg

2025-02-14T21:06:31Z

Make sure the compare value in the lr/sc loop is sign extended to match what lr.w does. Fortunately, due to the compiler keeping the register contents sign extended anyway the lack of the explicit extension didn't result in wrong code so far, but this cannot be relied upon. Fixes: b90edb33010b ("RISC-V: Add futex support.") Signed-off-by: Andreas Schwab Reviewed-by: Alexandre Ghiti Reviewed-by: Björn Töpel Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/mvmfrkv2vhz.fsf@suse.de Signed-off-by: Palmer Dabbelt

riscv/futex: Optimize atomic cmpxchg

2024-12-11T15:09:55Z

Remove redundant release/acquire barriers, optimizing the lr/sc sequence to provide conditional RCsc synchronization, per the RVWMO. Signed-off-by: Davidlohr Bueso Reviewed-by: Andrea Parri Link: https://lore.kernel.org/r/20241113183321.491113-1-dave@stgolabs.net Signed-off-by: Palmer Dabbelt

riscv: extable: add a dedicated uaccess handler

2022-01-06T01:53:29Z

Inspired by commit 2e77a62cb3a6 ("arm64: extable: add a dedicated uaccess handler"), do similar to riscv to add a dedicated uaccess exception handler to update registers in exception context and subsequently return back into the function which faulted, so we remove the need for fixups specialized to each faulting instruction. Signed-off-by: Jisheng Zhang Signed-off-by: Palmer Dabbelt

riscv: extable: consolidate definitions

2022-01-06T01:52:47Z

This is a riscv port of commit 819771cc2892 ("arm64: extable: consolidate definitions"). Signed-off-by: Jisheng Zhang Signed-off-by: Palmer Dabbelt

riscv: consolidate __ex_table construction

2022-01-06T01:52:15Z

Consolidate all the __ex_table constuction code with a _ASM_EXTABLE helper. There should be no functional change as a result of this patch. Signed-off-by: Jisheng Zhang Reviewed-by: Kefeng Wang Signed-off-by: Palmer Dabbelt

futex: arch_futex_atomic_op_inuser() calling conventions change

2020-03-28T03:58:51Z

Move access_ok() in and pagefault_enable()/pagefault_disable() out. Mechanical conversion only - some instances don't really need a separate access_ok() at all (e.g. the ones only using get_user()/put_user(), or architectures where access_ok() is always true); we'll deal with that in followups. Signed-off-by: Al Viro

Merge branch 'next/nommu' into for-next

2019-11-23T02:59:09Z

Conflicts: arch/riscv/boot/Makefile arch/riscv/include/asm/sbi.h

riscv: add nommu support

2019-11-17T23:17:39Z

The kernel runs in M-mode without using page tables, and thus can't run bare metal without help from additional firmware. Most of the patch is just stubbing out code not needed without page tables, but there is an interesting detail in the signals implementation: - The normal RISC-V syscall ABI only implements rt_sigreturn as VDSO entry point, but the ELF VDSO is not supported for nommu Linux. We instead copy the code to call the syscall onto the stack. In addition to enabling the nommu code a new defconfig for a small kernel image that can run in nommu mode on qemu is also provided, to run a kernel in qemu you can use the following command line: qemu-system-riscv64 -smp 2 -m 64 -machine virt -nographic \ -kernel arch/riscv/boot/loader \ -drive file=rootfs.ext2,format=raw,id=hd0 \ -device virtio-blk-device,drive=hd0 Contains contributions from Damien Le Moal . Signed-off-by: Christoph Hellwig Reviewed-by: Anup Patel [paul.walmsley@sifive.com: updated to apply; add CONFIG_MMU guards around PCI_IOBASE definition to fix build issues; fixed checkpatch issues; move the PCI_IO_* and VMEMMAP address space macros along with the others; resolve sparse warning] Signed-off-by: Paul Walmsley

riscv: clean up the macro format in each header file

2019-11-12T20:04:52Z

There are many different formats in each header now, such as _ASM_XXX_H, __ASM_XXX_H, _ASM_RISCV_XXX_H, RISCV_XXX_H, etc., This patch tries to unify the format by using _ASM_RISCV_XXX_H, because the most header use it now. This patch also adds the conditional to the headers if they lost it. Signed-off-by: Zong Li Signed-off-by: Paul Walmsley

riscv: remove CONFIG_RISCV_ISA_A

2019-04-25T21:51:10Z

This option is always enabled, and not supporting the A extensions would create a complete ABI trainwreck, so there is no point in even slightly encouraging such an idea by keeping this unselectable code around. Signed-off-by: Christoph Hellwig Signed-off-by: Palmer Dabbelt