RISC-V: __test_and_op_bit_ord should be strongly ordered

2017-11-28T22:04:05Z

I mis-read the documentation. After looking at it again the documentation is actually as clear as it can be, it's just that I didn't actually read it in order and therefor did the wrong thing. Signed-off-by: Palmer Dabbelt

RISC-V: Atomic and Locking Code

2017-09-26T22:26:45Z

This contains all the code that directly interfaces with the RISC-V memory model. While this code corforms to the current RISC-V ISA specifications (user 2.2 and priv 1.10), the memory model is somewhat underspecified in those documents. There is a working group that hopes to produce a formal memory model by the end of the year, but my understanding is that the basic definitions we're relying on here won't change significantly. Reviewed-by: Arnd Bergmann Signed-off-by: Palmer Dabbelt

kernel/arch/riscv/include/asm/bitops.h, branch linux-5.1.y

RISC-V: __test_and_op_bit_ord should be strongly ordered

RISC-V: Atomic and Locking Code