kernel/arch/powerpc/sysdev/xics/ics-opal.c, branch linux-5.1.y

powerpc: Use pr_warn instead of pr_warning

2017-12-04T00:54:34Z

At some point, pr_warning will be removed so all logging messages use a consistent _warn style. Update arch/powerpc/ Miscellanea: o Coalesce formats o Realign arguments o Use %s, __func__ instead of embedded function names o Remove unnecessary line continuations Signed-off-by: Joe Perches Acked-by: Geoff Levand [mpe: Rebase due to some %pOF changes.] Signed-off-by: Michael Ellerman

powerpc/xics: Properly set Edge/Level type and enable resend

2016-08-09T04:50:18Z

This sets the type of the interrupt appropriately. We set it as follow: - If not mapped from the device-tree, we use edge. This is the case of the virtual interrupts and PCI MSIs for example. - If mapped from the device-tree and #interrupt-cells is 2 (PAPR compliant), we use the second cell to set the appropriate type - If mapped from the device-tree and #interrupt-cells is 1 (current OPAL on P8 does that), we assume level sensitive since those are typically going to be the PSI LSIs which are level sensitive. Additionally, we mark the interrupts requested via the opal_interrupts property all level. This is a bit fishy but the best we can do until we fix OPAL to properly expose them with a complete descriptor. It is also correct for the current HW anyway as OPAL interrupts are currently PCI error and PSI interrupts which are level. Finally now that edge interrupts are properly identified, we can enable CONFIG_HARDIRQS_SW_RESEND which will make the core re-send them if they occur while masked, which some drivers rely upon. This fixes issues with lost interrupts on some Mellanox adapters. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Ellerman

powerpc, irq: Use access helper irq_data_get_affinity_mask()

2015-09-15T15:06:28Z

Use access helper irq_data_get_affinity_mask() so we can move the affinity mask to irq_common_data. Signed-off-by: Jiang Liu Cc: Benjamin Herrenschmidt Cc: Michael Ellerman Cc: linuxppc-dev@lists.ozlabs.org Link: http://lkml.kernel.org/r/1433145945-789-25-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner

treewide: Use helper function to access irq_data->msi_desc

2015-07-16T21:31:37Z

Use irq_data access helper to access irq_data->msi_desc, so we can move msi_desc from struct irq_data into struct irq_common_data later. Signed-off-by: Jiang Liu Cc: Bjorn Helgaas Cc: Tony Luck Cc: Fenghua Yu Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: Michael Ellerman Cc: Chris Metcalf Signed-off-by: Thomas Gleixner

powerpc: use %*pb[l] to print bitmaps including cpumasks and nodemasks

2015-02-14T05:21:36Z

printk and friends can now format bitmaps using '%*pb[l]'. cpumask and nodemask also provide cpumask_pr_args() and nodemask_pr_args() respectively which can be used to generate the two printf arguments necessary to format the specified cpu/nodemask. * Spurious if (len > 1) test dropped from shared_cpu_map_show(). Signed-off-by: Tejun Heo Cc: Benjamin Herrenschmidt Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

PCI/MSI: Rename mask/unmask_msi_irq treewide

2014-11-23T12:01:45Z

The PCI/MSI irq chip callbacks mask/unmask_msi_irq have been renamed to pci_msi_mask/unmask_irq to mark them PCI specific. Rename all usage sites. The conversion helper functions are kept around to avoid conflicts in next and will be removed after merging into mainline. Coccinelle assisted conversion. No functional change. Signed-off-by: Thomas Gleixner Cc: Bjorn Helgaas Cc: Russell King Cc: Ralf Baechle Cc: Benjamin Herrenschmidt Cc: Heiko Carstens Cc: "David S. Miller" Cc: Chris Metcalf Cc: x86@kernel.org Cc: Jiang Liu Cc: Jason Cooper Cc: Murali Karicheri Cc: Thierry Reding Cc: Mohit Kumar Cc: Simon Horman Cc: Michal Simek Cc: Yijing Wang

powerpc/powernv: Fix endian issues in OPAL ICS backend

2013-10-11T05:48:46Z

Signed-off-by: Benjamin Herrenschmidt

powerpc: Fix irq_set_affinity() return values

2013-05-14T06:00:18Z

Signed-off-by: Alexander Gordeev Signed-off-by: Benjamin Herrenschmidt

powerpc/powernv: Add OPAL ICS backend

2011-09-20T06:09:59Z

OPAL handles HW access to the various ICS or equivalent chips for us (with the exception of p5ioc2 based HEA which uses a different backend) similarily to what RTAS does on pSeries. Signed-off-by: Benjamin Herrenschmidt