<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/arch/powerpc/include/asm/xive.h, branch linux-6.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2021-08-10T13:15:02Z</updated>
<entry>
<title>KVM: PPC: Book3S HV: XIVE: Add support for automatic save-restore</title>
<updated>2021-08-10T13:15:02Z</updated>
<author>
<name>Cédric Le Goater</name>
<email>clg@kaod.org</email>
</author>
<published>2021-07-20T13:42:09Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=f5af0a978776b710f16dc99a85496b1e760bf9e0'/>
<id>urn:sha1:f5af0a978776b710f16dc99a85496b1e760bf9e0</id>
<content type='text'>
On P10, the feature doing an automatic "save &amp; restore" of a VCPU
interrupt context is set by default in OPAL. When a VP context is
pulled out, the state of the interrupt registers are saved by the XIVE
interrupt controller under the internal NVP structure representing the
VP. This saves a costly store/load in guest entries and exits.

If OPAL advertises the "save &amp; restore" feature in the device tree,
it should also have set the 'H' bit in the CAM line. Check that when
vCPUs are connected to their ICP in KVM before going any further.

Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20210720134209.256133-3-clg@kaod.org

</content>
</entry>
<entry>
<title>powerpc/pseries/pci: Add a msi_free() handler to clear XIVE data</title>
<updated>2021-08-10T13:14:58Z</updated>
<author>
<name>Cédric Le Goater</name>
<email>clg@kaod.org</email>
</author>
<published>2021-07-01T13:27:27Z</published>
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<id>urn:sha1:9a014f456881e947bf8cdd8c984a207097e6c096</id>
<content type='text'>
The MSI domain clears the IRQ with msi_domain_free(), which calls
irq_domain_free_irqs_top(), which clears the handler data. This is a
problem for the XIVE controller since we need to unmap MMIO pages and
free a specific XIVE structure.

The 'msi_free()' handler is called before irq_domain_free_irqs_top()
when the handler data is still available. Use that to clear the XIVE
controller data.

Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20210701132750.1475580-10-clg@kaod.org

</content>
</entry>
<entry>
<title>powerpc/xive: Simplify the dump of XIVE interrupts under xmon</title>
<updated>2021-04-14T13:04:14Z</updated>
<author>
<name>Cédric Le Goater</name>
<email>clg@kaod.org</email>
</author>
<published>2021-03-31T14:45:11Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=6bf66eb8f404050030805c65cf39a810892f5f8e'/>
<id>urn:sha1:6bf66eb8f404050030805c65cf39a810892f5f8e</id>
<content type='text'>
Move the xmon routine under XIVE subsystem and rework the loop on the
interrupts taking into account the xive_irq_domain to filter out IPIs.

Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Reviewed-by: Greg Kurz &lt;groug@kaod.org&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20210331144514.892250-7-clg@kaod.org
</content>
</entry>
<entry>
<title>powerpc/xive: Remove P9 DD1 flag XIVE_IRQ_FLAG_EOI_FW</title>
<updated>2020-12-10T22:53:10Z</updated>
<author>
<name>Cédric Le Goater</name>
<email>clg@kaod.org</email>
</author>
<published>2020-12-10T17:14:47Z</published>
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<id>urn:sha1:cf58b746665d0177b86d42d18e60985fa1fdb909</id>
<content type='text'>
This flag was used to support the P9 DD1 and we have stopped
supporting this CPU when DD2 came out. See skiboot commit:

  https://github.com/open-power/skiboot/commit/0b0d15e3c170

Also, remove eoi handler which is now unused.

Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Reviewed-by: Greg Kurz &lt;groug@kaod.org&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20201210171450.1933725-11-clg@kaod.org
</content>
</entry>
<entry>
<title>powerpc/xive: Remove P9 DD1 flag XIVE_IRQ_FLAG_MASK_FW</title>
<updated>2020-12-10T22:53:10Z</updated>
<author>
<name>Cédric Le Goater</name>
<email>clg@kaod.org</email>
</author>
<published>2020-12-10T17:14:46Z</published>
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<id>urn:sha1:b5277d18c65e31ce51f6733ebdca3985a962fab5</id>
<content type='text'>
This flag was used to support the PHB4 LSIs on P9 DD1 and we have
stopped supporting this CPU when DD2 came out. See skiboot commit:

  https://github.com/open-power/skiboot/commit/0b0d15e3c170

Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Reviewed-by: Greg Kurz &lt;groug@kaod.org&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20201210171450.1933725-10-clg@kaod.org
</content>
</entry>
<entry>
<title>powerpc/xive: Remove P9 DD1 flag XIVE_IRQ_FLAG_SHIFT_BUG</title>
<updated>2020-12-10T22:53:10Z</updated>
<author>
<name>Cédric Le Goater</name>
<email>clg@kaod.org</email>
</author>
<published>2020-12-10T17:14:45Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=4cc0e36df2c0a41fd38645ddde08d2bfba699b7a'/>
<id>urn:sha1:4cc0e36df2c0a41fd38645ddde08d2bfba699b7a</id>
<content type='text'>
This flag was used to support the PHB4 LSIs on P9 DD1 and we have
stopped supporting this CPU when DD2 came out. See skiboot commit:

  https://github.com/open-power/skiboot/commit/0b0d15e3c170

Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Reviewed-by: Greg Kurz &lt;groug@kaod.org&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20201210171450.1933725-9-clg@kaod.org
</content>
</entry>
<entry>
<title>powerpc/xive: Rename XIVE_IRQ_NO_EOI to show its a flag</title>
<updated>2020-12-10T22:34:07Z</updated>
<author>
<name>Cédric Le Goater</name>
<email>clg@kaod.org</email>
</author>
<published>2020-12-10T17:14:39Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=4f1c3f7b08187e6b97701c7fb2dc6f3749566c62'/>
<id>urn:sha1:4f1c3f7b08187e6b97701c7fb2dc6f3749566c62</id>
<content type='text'>
This is a simple cleanup to identify easily all flags of the XIVE
interrupt structure. The interrupts flagged with XIVE_IRQ_FLAG_NO_EOI
are the escalations used to wake up vCPUs in KVM. They are handled
very differently from the rest.

Signed-off-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Reviewed-by: Greg Kurz &lt;groug@kaod.org&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20201210171450.1933725-3-clg@kaod.org
</content>
</entry>
<entry>
<title>powerpc/xive: Remove unused inline function xive_kexec_teardown_cpu()</title>
<updated>2020-07-16T03:12:44Z</updated>
<author>
<name>YueHaibing</name>
<email>yuehaibing@huawei.com</email>
</author>
<published>2020-07-15T02:50:40Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=29d9407e1037868b59d12948d42ad3ef58fc3a5a'/>
<id>urn:sha1:29d9407e1037868b59d12948d42ad3ef58fc3a5a</id>
<content type='text'>
commit e27e0a94651e ("powerpc/xive: Remove xive_kexec_teardown_cpu()")
left behind this, remove it.

Signed-off-by: YueHaibing &lt;yuehaibing@huawei.com&gt;
Reviewed-by: Greg Kurz &lt;groug@kaod.org&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20200715025040.33952-1-yuehaibing@huawei.com
</content>
</entry>
<entry>
<title>powerpc/xive: Define xive_native_alloc_irq_on_chip()</title>
<updated>2020-04-20T06:52:59Z</updated>
<author>
<name>Haren Myneni</name>
<email>haren@linux.ibm.com</email>
</author>
<published>2020-04-16T05:58:40Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=8d0ea29db5aefd0d94fa4b6ca6124c68998f3c6a'/>
<id>urn:sha1:8d0ea29db5aefd0d94fa4b6ca6124c68998f3c6a</id>
<content type='text'>
This function allocates IRQ on a specific chip. VAS needs per chip
IRQ allocation and will have IRQ handler per VAS instance.

Signed-off-by: Haren Myneni &lt;haren@linux.ibm.com&gt;
Reviewed-by: Cédric Le Goater &lt;clg@kaod.org&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/1587016720.2275.1047.camel@hbabu-laptop
</content>
</entry>
<entry>
<title>powerpc/xive: Drop extern qualifiers from header function prototypes</title>
<updated>2020-01-23T10:31:23Z</updated>
<author>
<name>Greg Kurz</name>
<email>groug@kaod.org</email>
</author>
<published>2019-11-15T18:10:58Z</published>
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<id>urn:sha1:b059c63620fbba8a5da60f01d99d003681447e3c</id>
<content type='text'>
As reported by ./scripts/checkpatch.pl --strict:

CHECK: extern prototypes should be avoided in .h files

Signed-off-by: Greg Kurz &lt;groug@kaod.org&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/157384145834.181768.944827793193636924.stgit@bahia.lan
</content>
</entry>
</feed>
