kernel/arch/powerpc/boot/4xx.c, branch linux-rolling-stable

powerpc/boot: Remove all 40x platforms from boot

2024-06-28T12:28:47Z

Remove 40x platforms from the boot directory. Signed-off-by: Christophe Leroy Signed-off-by: Michael Ellerman Link: https://msgid.link/20240628121201.130802-2-mpe@ellerman.id.au

powerpc/44x: Adjust indentation in ibm4xx_denali_fixup_memsize

2020-01-06T05:25:27Z

Clang warns: ../arch/powerpc/boot/4xx.c:231:3: warning: misleading indentation; statement is not part of the previous 'else' [-Wmisleading-indentation] val = SDRAM0_READ(DDR0_42); ^ ../arch/powerpc/boot/4xx.c:227:2: note: previous statement is here else ^ This is because there is a space at the beginning of this line; remove it so that the indentation is consistent according to the Linux kernel coding style and clang no longer warns. Fixes: d23f5099297c ("[POWERPC] 4xx: Adds decoding of 440SPE memory size to boot wrapper library") Signed-off-by: Nathan Chancellor Reviewed-by: Nick Desaulniers Signed-off-by: Michael Ellerman Link: https://github.com/ClangBuiltLinux/linux/issues/780 Link: https://lore.kernel.org/r/20191209200338.12546-1-natechancellor@gmail.com

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-05-30T18:26:32Z

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman

powerpc/44x: Fix mask and shift to zero bug

2017-08-31T04:26:06Z

My static checker complains that 0x00001800 >> 13 is zero. Looking at the context, it seems like a copy and paste bug from the line below and probably 0x3 << 13 or 0x00006000 was intended. Fixes: 2af59f7d5c3e ("[POWERPC] 4xx: Add 405GPr and 405EP support in boot wrapper") Signed-off-by: Dan Carpenter Acked-by: Benjamin Herrenschmidt Signed-off-by: Michael Ellerman

powerpc/44x: Fix UART clocks on 440SPe

2010-05-12T11:48:49Z

The code to fixup the serial ports on 440SPe uses the incorrect addresses for these. This fixes it. Signed-off-by: Benjamin Herrenschmidt Acked-by: Stefan Roese Signed-off-by: Josh Boyer

powerpc/405ex: provide necessary fixup function to support cuImage

2009-08-31T13:20:55Z

For cuImage format it's necessary to provide clock fixups since u-boot will not pass necessary clock frequency into the dtb included into cuImage so we implement the clock fixups as defined in the technical documentation for the board and update header file with the basic register definitions. Signed-off-by: Tiejun Chen Signed-off-by: Josh Boyer

powerpc/44x: Correct memory size calculation for denali-based boards

2009-04-24T13:02:37Z

Some U-Boot versions incorrectly set the number of chipselects to two for Sequoia/Rainier boards while they only have one chipselect hardwired. This patch adds a workaround for this, hardcoding the number of chipselects to one for sequioa/rainer board models and reading the actual value from the memory controller register DDR0_10 otherwise. It also fixes another error in the way ibm4xx_denali_fixup_memsize calculates memory size. When testing the DDR_REDUC bit, the polarity is backwards. A "1" implies 32-bit wide memory while a "0" implies 64-bit wide memory. Signed-off-by: Mikhail Zolotaryov Signed-off-by: Valentine Barshak Signed-off-by: Steven A. Falco Acked-by: Stefan Roese Signed-off-by: Josh Boyer

[POWERPC] 4xx: Workaround for CHIP_11 Errata

2008-05-19T14:36:40Z

The PowerPC 440EP, 440GR, 440EPx, and 440GRx chips have an issue that causes the PLB3-to-PLB4 bridge to wait indefinitely for transaction requests that cross the end-of-memory-range boundary. Since the DDR controller only returns the valid portion of a read request, the bridge will prevent other PLB masters from completing their transactions. This implements the recommended workaround for this errata for chips that use older versions of firmware that do not already handle it. The last 4KiB of memory are hidden from the kernel to prevent the problem transactions from occurring. Signed-off-by: Josh Boyer Acked-by: Stefan Roese Signed-off-by: Josh Boyer

[POWERPC] 4xx: logical/bitand typo in powerpc/boot/4xx.c

2008-01-25T13:13:39Z

logical/bitand typo Signed-off-by: Roel Kluin <12o3l@tiscali.nl> Signed-off-by: Josh Boyer

[POWERPC] 4xx: Add 405GPr and 405EP support in boot wrapper

2008-01-08T13:58:09Z

This patch adds support for 405GPr processors with optional new mode strapping. ibm405gp_fixup_clocks() can now be used for 405GP and 405GPr CPUs. This is in preparation of porting the cpci405 platform support from arch/ppc to arch/powerpc. This patch also adds ibm405ep_fixup_clocks() to support 405EP CPUs from the boot wrapper. Signed-off-by: Matthias Fuchs Signed-off-by: Josh Boyer