kernel/arch/powerpc/boot/4xx.c, branch linux-4.3.y

powerpc/44x: Fix UART clocks on 440SPe

2010-05-12T11:48:49Z

The code to fixup the serial ports on 440SPe uses the incorrect addresses for these. This fixes it. Signed-off-by: Benjamin Herrenschmidt Acked-by: Stefan Roese Signed-off-by: Josh Boyer

powerpc/405ex: provide necessary fixup function to support cuImage

2009-08-31T13:20:55Z

For cuImage format it's necessary to provide clock fixups since u-boot will not pass necessary clock frequency into the dtb included into cuImage so we implement the clock fixups as defined in the technical documentation for the board and update header file with the basic register definitions. Signed-off-by: Tiejun Chen Signed-off-by: Josh Boyer

powerpc/44x: Correct memory size calculation for denali-based boards

2009-04-24T13:02:37Z

Some U-Boot versions incorrectly set the number of chipselects to two for Sequoia/Rainier boards while they only have one chipselect hardwired. This patch adds a workaround for this, hardcoding the number of chipselects to one for sequioa/rainer board models and reading the actual value from the memory controller register DDR0_10 otherwise. It also fixes another error in the way ibm4xx_denali_fixup_memsize calculates memory size. When testing the DDR_REDUC bit, the polarity is backwards. A "1" implies 32-bit wide memory while a "0" implies 64-bit wide memory. Signed-off-by: Mikhail Zolotaryov Signed-off-by: Valentine Barshak Signed-off-by: Steven A. Falco Acked-by: Stefan Roese Signed-off-by: Josh Boyer

[POWERPC] 4xx: Workaround for CHIP_11 Errata

2008-05-19T14:36:40Z

The PowerPC 440EP, 440GR, 440EPx, and 440GRx chips have an issue that causes the PLB3-to-PLB4 bridge to wait indefinitely for transaction requests that cross the end-of-memory-range boundary. Since the DDR controller only returns the valid portion of a read request, the bridge will prevent other PLB masters from completing their transactions. This implements the recommended workaround for this errata for chips that use older versions of firmware that do not already handle it. The last 4KiB of memory are hidden from the kernel to prevent the problem transactions from occurring. Signed-off-by: Josh Boyer Acked-by: Stefan Roese Signed-off-by: Josh Boyer

[POWERPC] 4xx: logical/bitand typo in powerpc/boot/4xx.c

2008-01-25T13:13:39Z

logical/bitand typo Signed-off-by: Roel Kluin <12o3l@tiscali.nl> Signed-off-by: Josh Boyer

[POWERPC] 4xx: Add 405GPr and 405EP support in boot wrapper

2008-01-08T13:58:09Z

This patch adds support for 405GPr processors with optional new mode strapping. ibm405gp_fixup_clocks() can now be used for 405GP and 405GPr CPUs. This is in preparation of porting the cpci405 platform support from arch/ppc to arch/powerpc. This patch also adds ibm405ep_fixup_clocks() to support 405EP CPUs from the boot wrapper. Signed-off-by: Matthias Fuchs Signed-off-by: Josh Boyer

[POWERPC] 4xx: Minor coding style cleanups for 4xx bootwrapper

2007-12-25T01:46:06Z

Remove some unneeded braces and make a busy loop more obvious. Signed-off-by: Josh Boyer

[POWERPC] 4xx: Rework clock probing in boot wrapper

2007-12-23T19:14:48Z

This reworks the boot wrapper library function that probes the chip clocks. Better separate the base function that is used on 440GX,SPe,EP,... from the uart fixups as those need different device-tree path on different processors. Also, rework the function itself based on the arch/ppc code from Eugene Surovegin which I find more readable, and which handles one more bypass case. Also handle the subtle difference between 440EP/EPx and 440SPe/GX, on the former, PerClk is derived from the PLB clock while on the later, it's derived from the OPB. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Josh Boyer

[POWERPC] 4xx: Adds decoding of 440SPE memory size to boot wrapper library

2007-12-23T19:14:13Z

This adds a function to the bootwrapper 4xx library to decode memory size on 440SPE processors. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Josh Boyer

[POWERPC] 4xx: EP405 boards support for arch/powerpc

2007-12-23T19:13:14Z

Brings EP405 support to arch/powerpc. The IRQ routing for the CPLD comes from a device-tree property, PCI is working to the point where I can see the video card, USB device, and south bridge. This should work with both EP405 and EP405PC. I've not totally figured out how IRQs are wired on this hardware though, thus at this stage, expect only USB interrupts working, pretty much the same as what arch/ppc did. Also, the flash, nvram, rtc and temp control still have to be wired. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Josh Boyer