kernel/arch/parisc/include/asm/spinlock.h, branch linux-rolling-stable

parisc: Fix lightweight spinlock checks to not break futexes

2023-08-16T16:32:18Z

commit a0f4b7879f2e14986200747d1b545e5daac8c624 upstream. The lightweight spinlock checks verify that a spinlock has either value 0 (spinlock locked) and that not any other bits than in __ARCH_SPIN_LOCK_UNLOCKED_VAL is set. This breaks the current LWS code, which writes the address of the lock into the lock word to unlock it, which was an optimization to save one assembler instruction. Fix it by making spinlock_types.h accessible for asm code, change the LWS spinlock-unlocking code to write __ARCH_SPIN_LOCK_UNLOCKED_VAL into the lock word, and add some missing lightweight spinlock checks to the LWS path. Finally, make the spinlock checks dependend on DEBUG_KERNEL. Noticed-by: John David Anglin Signed-off-by: Helge Deller Tested-by: John David Anglin Cc: stable@vger.kernel.org # v6.4+ Fixes: 15e64ef6520e ("parisc: Add lightweight spinlock checks") Signed-off-by: Greg Kroah-Hartman

parisc: Add lightweight spinlock checks

2023-05-24T12:23:07Z

Add a lightweight spinlock check which uses only two instructions per spinlock call. It detects if a spinlock has been trashed by some memory corruption and then halts the kernel. It will not detect uninitialized spinlocks, for which CONFIG_DEBUG_SPINLOCK needs to be enabled. This lightweight spinlock check shouldn't influence runtime, so it's safe to enable it by default. The __ARCH_SPIN_LOCK_UNLOCKED_VAL constant has been choosen small enough to be able to be loaded by one LDI assembler statement. Signed-off-by: Helge Deller

locking: Remove spin_lock_flags() etc

2021-10-30T14:37:28Z

parisc, ia64 and powerpc32 are the only remaining architectures that provide custom arch_{spin,read,write}_lock_flags() functions, which are meant to re-enable interrupts while waiting for a spinlock. However, none of these can actually run into this codepath, because it is only called on architectures without CONFIG_GENERIC_LOCKBREAK, or when CONFIG_DEBUG_LOCK_ALLOC is set without CONFIG_LOCKDEP, and none of those combinations are possible on the three architectures. Going back in the git history, it appears that arch/mn10300 may have been able to run into this code path, but there is a good chance that it never worked. On the architectures that still exist, it was already impossible to hit back in 2008 after the introduction of CONFIG_GENERIC_LOCKBREAK, and possibly earlier. As this is all dead code, just remove it and the helper functions built around it. For arch/ia64, the inline asm could be cleaned up, but it seems safer to leave it untouched. Signed-off-by: Arnd Bergmann Signed-off-by: Peter Zijlstra (Intel) Acked-by: Helge Deller # parisc Link: https://lore.kernel.org/r/20211022120058.1031690-1-arnd@kernel.org

parisc: Improve spinlock handling

2020-10-15T06:10:39Z

Use READ_ONCE() to check if spinlock is locked. The other changes are cleanups. Signed-off-by: John David Anglin Signed-off-by: Helge Deller

Revert "parisc: Revert "Release spinlocks using ordered store""

2020-07-28T16:56:14Z

This reverts commit 86d4d068df573a8c2105554624796c086d6bec3d. Signed-off-by: Helge Deller Cc: # v5.0+

Revert "parisc: Use ldcw instruction for SMP spinlock release barrier"

2020-07-28T16:54:40Z

This reverts commit 9e5c602186a692a7e848c0da17aed40f49d30519. No need to use the ldcw instruction as SMP spinlock release barrier. Revert it to gain back speed again. Signed-off-by: Helge Deller Cc: # v5.2+

Revert "parisc: Improve interrupt handling in arch_spin_lock_flags()"

2020-07-28T16:49:45Z

This reverts commit 2772f0efd5bbd5413db3d22e363b779ca0fa5310. It turns out that we want to implement the spinlock code differently. Signed-off-by: Helge Deller Cc: # v5.7+

parisc: Rework arch_rw locking functions

2020-04-05T20:29:55Z

Clean up the arch read/write locking functions based on the arc implemenation. This improves readability of those functions. Signed-off-by: Helge Deller

parisc: Improve interrupt handling in arch_spin_lock_flags()

2020-04-05T20:16:38Z

Rewrite arch_spin_lock() and arch_spin_lock_flags() to not re-enable and disable the PSW_SM_I interrupt flag too often. Signed-off-by: Helge Deller

parisc: Use ldcw instruction for SMP spinlock release barrier

2019-05-03T21:47:40Z

There are only a couple of instructions that can function as a memory barrier on parisc. Currently, we use the sync instruction as a memory barrier when releasing a spinlock. However, the ldcw instruction is a better barrier when we have a handy memory location since it operates in the cache on coherent machines. This patch updates the spinlock release code to use ldcw. I also changed the "stw,ma" instructions to "stw" instructions as it is not an adequate barrier. Signed-off-by: John David Anglin Signed-off-by: Helge Deller