kernel/arch/openrisc/include/asm/pgtable.h, branch linux-5.1.y

openrisc: add cacheflush support to fix icache aliasing

2017-11-03T05:01:15Z

On OpenRISC the icache does not snoop data stores. This can cause aliasing as reported by Jan. This patch fixes the issue to ensure icache is properly synchronized when code is written to memory. It supports both SMP and UP flushing. This supports dcache flush as well for architectures that do not support write-through caches; most OpenRISC implementations do implement write-through cache however. Dcache flushes are done only on a single core as OpenRISC dcaches all support snooping of bus stores. Signed-off-by: Jan Henrik Weinstock [shorne@gmail.com: Squashed patches and wrote commit message] Signed-off-by: Stafford Horne

openrisc: initial SMP support

2017-11-03T05:01:13Z

This patch introduces the SMP support for the OpenRISC architecture. The SMP architecture requires cores which have multi-core features which have been introduced a few years back including: - New SPRS SPR_COREID SPR_NUMCORES - Shadow SPRs - Atomic Instructions - Cache Coherency - A wired in IPI controller This patch adds all of the SMP specific changes to core infrastructure, it looks big but it needs to go all together as its hard to split this one up. Boot loader spinning of second cpu is not supported yet, it's assumed that Linux is booted straight after cpu reset. The bulk of these changes are trivial changes to refactor to use per cpu data structures throughout. The addition of the smp.c and changes in time.c are the changes. Some specific notes: MM changes ---------- The reason why this is created as an array, and not with DEFINE_PER_CPU is that doing it this way, we'll save a load in the tlb-miss handler (the load from __per_cpu_offset). TLB Flush --------- The SMP implementation of flush_tlb_* works by sending out a function-call IPI to all the non-local cpus by using the generic on_each_cpu() function. Currently, all flush_tlb_* functions will result in a flush_tlb_all(), which has always been the behaviour in the UP case. CPU INFO -------- This creates a per cpu cpuinfo struct and fills it out accordingly for each activated cpu. show_cpuinfo is also updated to reflect new version information in later versions of the spec. SMP API ------- This imitates the arm64 implementation by having a smp_cross_call callback that can be set by set_smp_cross_call to initiate an IPI and a handle_IPI function that is expected to be called from an IPI irqchip driver. Signed-off-by: Stefan Kristiansson [shorne@gmail.com: added cpu stop, checkpatch fixes, wrote commit message] Signed-off-by: Stafford Horne

openrisc: add forward declaration for struct vm_area_struct

2017-09-10T22:22:05Z

After removing linux/vmalloc.h from asm-generic/io.h, the following warning occurs on openrisc: In file included from arch/openrisc/include/asm/io.h:33:0, from include/linux/io.h:25, from drivers/tty/serial/earlycon.c:19: arch/openrisc/include/asm/pgtable.h:424:2: warning: 'struct vm_area_struct' declared inside parameter list unsigned long address, pte_t *pte) ^ arch/openrisc/include/asm/pgtable.h:424:2: warning: its scope is only this definition or declaration, which is probably not what you want Reported-by: kbuild test robot Cc: Arnd Bergmann Signed-off-by: Tobias Klauser Signed-off-by: Stafford Horne

arch, mm: convert all architectures to use 5level-fixup.h

2017-03-09T19:48:47Z

If an architecture uses 4level-fixup.h we don't need to do anything as it includes 5level-fixup.h. If an architecture uses pgtable-nop*d.h, define __ARCH_USE_5LEVEL_HACK before inclusion of the header. It makes asm-generic code to use 5level-fixup.h. If an architecture has 4-level paging or folds levels on its own, include 5level-fixup.h directly. Signed-off-by: Kirill A. Shutemov Acked-by: Michal Hocko Signed-off-by: Linus Torvalds

openrisc: fix PTRS_PER_PGD define

2016-12-12T14:09:06Z

On OpenRISC, with its 8k pages, PAGE_SHIFT is defined to be 13. That makes the expression (1UL << (PAGE_SHIFT-2)) evaluate to 2048. The correct value for PTRS_PER_PGD should be 256. Correcting the PTRS_PER_PGD define unveiled a bug in map_ram(), where PTRS_PER_PGD was used when the intent was to iterate over a set of page table entries. This patch corrects that issue as well. Signed-off-by: Stefan Kristiansson Acked-by: Jonas Bonn Tested-by: Guenter Roeck Signed-off-by: Stafford Horne

mm: make FIRST_USER_ADDRESS unsigned long on all archs

2015-02-12T01:06:03Z

LKP has triggered a compiler warning after my recent patch "mm: account pmd page tables to the process": mm/mmap.c: In function 'exit_mmap': >> mm/mmap.c:2857:2: warning: right shift count >= width of type [enabled by default] The code: > 2857 WARN_ON(mm_nr_pmds(mm) > 2858 round_up(FIRST_USER_ADDRESS, PUD_SIZE) >> PUD_SHIFT); In this, on tile, we have FIRST_USER_ADDRESS defined as 0. round_up() has the same type -- int. PUD_SHIFT. I think the best way to fix it is to define FIRST_USER_ADDRESS as unsigned long. On every arch for consistency. Signed-off-by: Kirill A. Shutemov Reported-by: Wu Fengguang Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

openrisc: drop _PAGE_FILE and pte_file()-related helpers

2015-02-10T22:30:33Z

We've replaced remap_file_pages(2) implementation with emulation. Nobody creates non-linear mapping anymore. Signed-off-by: Kirill A. Shutemov Cc: Jonas Bonn Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

consolidate io_remap_pfn_range definitions

2013-06-29T08:46:35Z

Signed-off-by: Al Viro

Remove remaining bits of io_remap_page_range()

2012-03-23T23:58:31Z

Commit 33bf56106d9b ("feature removal of io_remap_page_range()") removed io_remap_page_range(), but it is still included in some arch header files. It has no in-tree users. Signed-off-by: Javi Merino Cc: Russell King Cc: Aurelien Jacquiot Cc: Michal Simek Cc: Jonas Bonn Cc: Randy Dunlap Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

OpenRISC: Memory management

2011-07-22T16:46:28Z

Signed-off-by: Jonas Bonn Reviewed-by: Arnd Bergmann