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<title>kernel/arch/mips/include/asm/uasm.h, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
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<updated>2023-12-11T01:21:40Z</updated>
<entry>
<title>mips: unhide uasm_in_compat_space_p() declaration</title>
<updated>2023-12-11T01:21:40Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2023-12-04T11:56:59Z</published>
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<id>urn:sha1:e9f98feb17207addcd66435d8211ccf9c0a563dd</id>
<content type='text'>
uasm_in_compat_space_p() has a conditional declaration but is defined
unconditionally because of another local user, which causes a warning:

arch/mips/mm/uasm.c:421:5: error: no previous prototype for 'uasm_in_compat_space_p' [-Werror=missing-prototypes]

Make the declaration unconditional to avoid this.

Link: https://lkml.kernel.org/r/20231204115710.2247097-10-arnd@kernel.org
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Cc: Stephen Rothwell &lt;sfr@rothwell.id.au&gt;
Cc: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
</content>
</entry>
<entry>
<title>mips, uasm: Add workaround for Loongson-2F nop CPU errata</title>
<updated>2021-10-06T19:28:09Z</updated>
<author>
<name>Johan Almbladh</name>
<email>johan.almbladh@anyfinetworks.com</email>
</author>
<published>2021-10-05T16:54:03Z</published>
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<id>urn:sha1:f7c036c15b5388749bc8de208fb7b19d69c4f6fa</id>
<content type='text'>
This patch implements a workaround for the Loongson-2F nop in generated,
code, if the existing option CONFIG_CPU_NOP_WORKAROUND is set. Before,
the binutils option -mfix-loongson2f-nop was enabled, but no workaround
was done when emitting MIPS code. Now, the nop pseudo instruction is
emitted as "or ax,ax,zero" instead of the default "sll zero,zero,0". This
is consistent with the workaround implemented by binutils.

Signed-off-by: Johan Almbladh &lt;johan.almbladh@anyfinetworks.com&gt;
Signed-off-by: Daniel Borkmann &lt;daniel@iogearbox.net&gt;
Signed-off-by: Andrii Nakryiko &lt;andrii@kernel.org&gt;
Reviewed-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Link: https://sourceware.org/legacy-ml/binutils/2009-11/msg00387.html
Link: https://lore.kernel.org/bpf/20211005165408.2305108-3-johan.almbladh@anyfinetworks.com
</content>
</entry>
<entry>
<title>mips, uasm: Enable muhu opcode for MIPS R6</title>
<updated>2021-10-06T19:28:02Z</updated>
<author>
<name>Tony Ambardar</name>
<email>Tony.Ambardar@gmail.com</email>
</author>
<published>2021-10-05T16:54:02Z</published>
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<id>urn:sha1:e737547eab6af8b57d77f7ba323c8d2d6b1a0008</id>
<content type='text'>
Enable the 'muhu' instruction, complementing the existing 'mulu', needed
to implement a MIPS32 BPF JIT.

Also fix a typo in the existing definition of 'dmulu'.

Signed-off-by: Tony Ambardar &lt;Tony.Ambardar@gmail.com&gt;
Signed-off-by: Johan Almbladh &lt;johan.almbladh@anyfinetworks.com&gt;
Signed-off-by: Daniel Borkmann &lt;daniel@iogearbox.net&gt;
Signed-off-by: Andrii Nakryiko &lt;andrii@kernel.org&gt;
Link: https://lore.kernel.org/bpf/20211005165408.2305108-2-johan.almbladh@anyfinetworks.com
</content>
</entry>
<entry>
<title>MIPS: uasm: Add div, mul and sel instructions for mipsr6</title>
<updated>2019-03-19T22:26:06Z</updated>
<author>
<name>Hassan Naveed</name>
<email>hnaveed@wavecomp.com</email>
</author>
<published>2019-03-12T22:47:56Z</published>
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<id>urn:sha1:0d1d17b9ff8e7d69b2169337b263822355404a86</id>
<content type='text'>
Add the following instructions for use by eBPF on mipsr6:
insn_ddivu_r6, insn_divu_r6, insn_dmodu, insn_dmulu, insn_modu,
insn_mulu, insn_seleqz, insn_selnez

Signed-off-by: Hassan Naveed &lt;hnaveed@wavecomp.com&gt;
Reviewed-by: Paul Burton &lt;paul.burton@mips.com&gt;
Signed-off-by: Paul Burton &lt;paul.burton@mips.com&gt;
Cc: kafai@fb.com
Cc: songliubraving@fb.com
Cc: yhs@fb.com
Cc: netdev@vger.kernel.org
Cc: bpf@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: James Hogan &lt;jhogan@kernel.org&gt;
Cc: Alexei Starovoitov &lt;ast@kernel.org&gt;
Cc: Daniel Borkmann &lt;daniel@iogearbox.net&gt;
Cc: open list:MIPS &lt;linux-mips@linux-mips.org&gt;
Cc: open list &lt;linux-kernel@vger.kernel.org&gt;
</content>
</entry>
<entry>
<title>mips: bpf: implement jitting of BPF_ALU | BPF_ARSH | BPF_X</title>
<updated>2018-12-07T21:30:48Z</updated>
<author>
<name>Jiong Wang</name>
<email>jiong.wang@netronome.com</email>
</author>
<published>2018-12-05T18:52:30Z</published>
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<id>urn:sha1:ee94b90c8acaa593b627f5f3fe93e076e7779f5c</id>
<content type='text'>
Jitting of BPF_K is supported already, but not BPF_X. This patch complete
the support for the latter on both MIPS and microMIPS.

Cc: Paul Burton &lt;paul.burton@mips.com&gt;
Cc: linux-mips@vger.kernel.org
Acked-by: Paul Burton &lt;paul.burton@mips.com&gt;
Signed-off-by: Jiong Wang &lt;jiong.wang@netronome.com&gt;
Signed-off-by: Alexei Starovoitov &lt;ast@kernel.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Add some instructions to uasm.</title>
<updated>2017-06-28T10:22:39Z</updated>
<author>
<name>David Daney</name>
<email>david.daney@cavium.com</email>
</author>
<published>2017-06-13T22:28:45Z</published>
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<id>urn:sha1:dc190129f1c16e025a42a9c3717de7ed47fc6e2f</id>
<content type='text'>
Follow on patches for eBPF JIT require these additional instructions:

   insn_bgtz, insn_blez, insn_break, insn_ddivu, insn_dmultu,
   insn_dsbh, insn_dshd, insn_dsllv, insn_dsra32, insn_dsrav,
   insn_dsrlv, insn_lbu, insn_movn, insn_movz, insn_multu, insn_nor,
   insn_sb, insn_sh, insn_slti, insn_dinsu, insn_lwu

... so, add them.

Sort the insn_* enumeration values alphabetically.

Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
Cc: Alexei Starovoitov &lt;ast@kernel.org&gt;
Cc: Daniel Borkmann &lt;daniel@iogearbox.net&gt;
Cc: Matt Redfearn &lt;matt.redfearn@imgtec.com&gt;
Cc: netdev@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16367/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: uasm: Remove needless ISA abstraction</title>
<updated>2017-04-12T11:52:21Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2017-03-30T21:52:15Z</published>
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<id>urn:sha1:33679a50370db9aa1a3f0cdf5f70c1c07236a4b2</id>
<content type='text'>
We always either target MIPS32/MIPS64 or microMIPS, and always include
one &amp; only one of uasm-mips.c or uasm-micromips.c. Therefore the
abstraction of the ISA in asm/uasm.h declaring functions for either ISA
is redundant &amp; needless. Remove it to simplify the code.

This is largely the result of the following:

  :%s/ISAOPC(\(.\{-}\))/uasm_i##\1/
  :%s/ISAFUNC(\(.\{-}\))/\1/

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Cc: Paul Burton &lt;paul.burton@imgtec.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/15844/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: uasm: Add support for LHU.</title>
<updated>2017-04-10T09:56:04Z</updated>
<author>
<name>David Daney</name>
<email>david.daney@cavium.com</email>
</author>
<published>2017-03-14T21:21:40Z</published>
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<id>urn:sha1:bfbfa9d61cf29f3579107892c7347c02d891dfec</id>
<content type='text'>
The follow-on BPF JIT patches use the LHU instruction, so add it.

Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
Cc: James Hogan &lt;james.hogan@imgtec.com&gt;
Cc: Alexei Starovoitov &lt;ast@kernel.org&gt;
Cc: Steven J. Hill &lt;steven.hill@cavium.com&gt;
Cc: linux-mips@linux-mips.org
Cc: netdev@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/15743/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: uasm: Add include guards in asm/uasm.h</title>
<updated>2017-02-03T15:19:01Z</updated>
<author>
<name>James Hogan</name>
<email>james.hogan@imgtec.com</email>
</author>
<published>2016-09-10T22:53:57Z</published>
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<id>urn:sha1:93a93c2461f9416a58c7d1e32fec201af8cc3aad</id>
<content type='text'>
Add include guards in asm/uasm.h to allow it to be safely used by a new
header asm/tlbex.h in the next patch to expose TLB exception building
functions for KVM to use.

Signed-off-by: James Hogan &lt;james.hogan@imgtec.com&gt;
Acked-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Cc: "Radim Krčmář" &lt;rkrcmar@redhat.com&gt;
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
</content>
</entry>
<entry>
<title>MIPS: uasm: Add MTHI/MTLO instructions</title>
<updated>2016-07-05T14:08:35Z</updated>
<author>
<name>James Hogan</name>
<email>james.hogan@imgtec.com</email>
</author>
<published>2016-06-23T16:34:37Z</published>
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<id>urn:sha1:9f730a60e5a046230cff8c9f4c8eb73f6dca7d81</id>
<content type='text'>
Add MTHI/MTLO instructions for writing to the hi &amp; lo registers to uasm
so that KVM can use uasm for generating its entry point code at runtime.

Signed-off-by: James Hogan &lt;james.hogan@imgtec.com&gt;
Acked-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
</content>
</entry>
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