kernel/arch/mips/include/asm/switch_to.h, branch linux-5.1.y

MIPS: Avoid FCSR sanitization when CONFIG_MIPS_FP_SUPPORT=n

2018-11-09T18:23:18Z

When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point, so we don't need to worry about floating point exceptions pending in the Floating point Control & Status Register (FCSR) during switch_to(). Stub out the __sanitize_fcr31() macro in this case. Signed-off-by: Paul Burton Patchwork: https://patchwork.linux-mips.org/patch/21010/ Cc: linux-mips@linux-mips.org

MIPS: Cleanup LLBit handling in switch_to

2017-01-03T15:34:42Z

Commit 7c151d3d5d7a ("MIPS: Make use of the ERETNC instruction on MIPS R6") began clearing LLBit during context switches, but did so on all systems where it is writable for unclear reasons & did so from a macro with "software_ll_bit" in its name, which is intended to operate on the ll_bit variable used by ll/sc emulation for old CPUs. We do now need to clear LLBit on MIPSr6 systems where we'll use eretnc to return to userland, but we don't need to do so on MIPSr5 systems with a writable LLBit. Move the clear to its own appropriately named macro, do it only for MIPSr6 systems & comment about why. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14409/ Signed-off-by: Ralf Baechle

MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue

2016-11-04T00:28:41Z

Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit 4249548454f7 ("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit 443c44032a54 ("MIPS: Always clear FCSR cause bits after emulation"), * commit 64bedffe4968 ("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki Cc: Paul Burton Cc: James Hogan Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle

MIPS: Fix watchpoint restoration

2016-05-09T10:00:02Z

Commit f51246efee2b ("MIPS: Get rid of finish_arch_switch().") moved the __restore_watch() call from finish_arch_switch() (i.e. after resume() returns) to before the resume() call in switch_to(). This results in watchpoints only being restored when a task is descheduled, preventing the watchpoints from being effective most of the time, except due to chance before the watchpoints are lazily removed. Fix the call sequence from switch_to() through to mips_install_watch_registers() to pass the task_struct pointer of the next task, instead of using current. This allows the watchpoints for the next (non-current) task to be restored without reintroducing finish_arch_switch(). Fixes: f51246efee2b ("MIPS: Get rid of finish_arch_switch().") Signed-off-by: James Hogan Cc: Paul Burton Cc: linux-mips@linux-mips.org Cc: # 4.3.x- Patchwork: https://patchwork.linux-mips.org/patch/12726/ Signed-off-by: Ralf Baechle

MIPS: Tidy up FPU context switching

2015-09-03T10:08:05Z

Rather than saving the scalar FP or vector context in the assembly resume function, reuse the existing C code we have in fpu.h to do exactly that. This reduces duplication, results in a much easier to read resume function & should allow the compiler to optimise out more MSA code due to is_msa_enabled()/cpu_has_msa being known-zero at compile time for kernels without MSA support. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin Cc: Maciej W. Rozycki Cc: linux-kernel@vger.kernel.org Cc: James Hogan Cc: Markos Chandras Cc: Manuel Lauss Patchwork: https://patchwork.linux-mips.org/patch/10830/ Signed-off-by: Ralf Baechle

MIPS: Get rid of finish_arch_switch().

2015-09-03T10:08:01Z

MIPS was using finish_arch_switch() as a hook to restore and initialize CPU context for all threads, even newly created kernel and user threads. This is however entirely solvable within switch_to() so get rid of finish_arch_switch() which is in the way of scheduler cleanups. Signed-off-by: Ralf Baechle

MIPS: MSA: bugfix - disable MSA correctly for new threads/processes.

2015-06-10T09:24:53Z

Due to the slightly odd way that new threads and processes start execution when scheduled for the very first time they were bypassing the required disable_msa call. Signed-off-by: Ralf Baechle

MIPS: Make use of the ERETNC instruction on MIPS R6

2015-02-17T15:37:37Z

The ERETNC instruction, introduced in MIPS R5, is similar to the ERET one, except it does not clear the LLB bit in the LLADDR register. This feature is necessary to safely emulate R2 LL/SC instructions. However, on context switches, we need to clear the LLAddr/LLB bit in order to make sure that an SC instruction from the new thread will never succeed if it happens to interrupt an LL operation on the same address from the previous thread. Signed-off-by: Markos Chandras

MIPS: COP2: CPP macro safety fixes.

2014-08-26T00:18:59Z

- Don't pass things to macros that couldn't be dereferences if that macro was actually a function. - Don't use empty function-like macros. Signed-off-by: Ralf Baechle

MIPS: Basic MSA context switching support

2014-03-26T22:09:10Z

This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle