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<title>kernel/arch/mips/include/asm/smp-cps.h, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
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<updated>2025-08-29T20:34:29Z</updated>
<entry>
<title>mips: Replace __ASSEMBLY__ with __ASSEMBLER__ in the mips headers</title>
<updated>2025-08-29T20:34:29Z</updated>
<author>
<name>Thomas Huth</name>
<email>thuth@redhat.com</email>
</author>
<published>2025-08-04T06:56:29Z</published>
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<id>urn:sha1:157f9533f9ffb5d9544515dcfe54e0901d9aa615</id>
<content type='text'>
While the GCC and Clang compilers already define __ASSEMBLER__
automatically when compiling assembler code, __ASSEMBLY__ is a macro
that only gets defined by the Makefiles in the kernel. Defining
such a macro was necessary in the early days of the kernel, since GCC
only started providing __ASSEMBLER__ since version 3.0 in 2000 (see
https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=f8f769ea4e69 ).
However, having two macros can be very confusing nowadays for the
developers when switching between userspace and kernelspace coding,
or when dealing with uapi headers that should use __ASSEMBLER__
instead. So let's now standardize on the __ASSEMBLER__ macro that is
provided by the compilers.

This is almost a completely mechanical patch (done with a simple
"sed -i" statement), with just one comment tweaked manually in
arch/mips/include/asm/cpu.h (that was missing some underscores).

Cc: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
Cc: linux-mips@vger.kernel.org
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Reviewed-by: Maciej W. Rozycki &lt;macro@orcam.me.uk&gt;
Signed-off-by: Thomas Huth &lt;thuth@redhat.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: CPS: Improve mips_cps_first_online_in_cluster()</title>
<updated>2025-07-16T16:34:49Z</updated>
<author>
<name>Gregory CLEMENT</name>
<email>gregory.clement@bootlin.com</email>
</author>
<published>2025-07-11T09:54:20Z</published>
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<id>urn:sha1:c71085f2c0f18f025784ce975358adcccaa8c041</id>
<content type='text'>
The initial implementation of this function goes through all the CPUs
in a cluster to determine if the current CPU is the only one
running. This process occurs every time the function is called.

However, during boot, we already perform this task, so let's take
advantage of this opportunity to create and fill a CPU bitmask that
can be easily and efficiently used later.

This patch modifies the function to allow providing the first
available online CPU when one already exists, which is necessary for
delay CPU calibration optimization.

Reviewed-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: CPS: Boot CPUs in secondary clusters</title>
<updated>2025-02-21T09:19:37Z</updated>
<author>
<name>Paul Burton</name>
<email>paulburton@kernel.org</email>
</author>
<published>2025-01-29T12:32:50Z</published>
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<id>urn:sha1:0856c143e1cd3ffd6ce10a72671335ca6a2cb841</id>
<content type='text'>
Probe for &amp; boot CPUs (cores &amp; VPs) in secondary clusters (ie. not the
cluster that began booting Linux) when they are present in systems with
CM 3.5 or higher.

Signed-off-by: Paul Burton &lt;paulburton@kernel.org&gt;
Signed-off-by: Chao-ying Fu &lt;cfu@wavecomp.com&gt;
Signed-off-by: Dragan Mladjenovic &lt;dragan.mladjenovic@syrmia.com&gt;
Signed-off-by: Aleksandar Rikalo &lt;arikalo@gmail.com&gt;
Tested-by: Serge Semin &lt;fancer.lancer@gmail.com&gt;
Tested-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: CPS: Introduce struct cluster_boot_config</title>
<updated>2025-02-21T09:19:34Z</updated>
<author>
<name>Paul Burton</name>
<email>paulburton@kernel.org</email>
</author>
<published>2025-01-29T12:32:49Z</published>
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<id>urn:sha1:75fa6a583882e8e09fa567eb3a3d8e115fa5c59f</id>
<content type='text'>
In preparation for supporting multi-cluster systems, introduce a struct
cluster_boot_config as an extra layer in the boot configuration
maintained by the MIPS Coherent Processing System (CPS) SMP
implementation. For now only one struct cluster_boot_config will be
allocated &amp; we'll simply defererence its core_config field to find the
struct core_boot_config array which can be used to boot as usual.

Signed-off-by: Paul Burton &lt;paulburton@kernel.org&gt;
Signed-off-by: Dragan Mladjenovic &lt;dragan.mladjenovic@syrmia.com&gt;
Signed-off-by: Aleksandar Rikalo &lt;arikalo@gmail.com&gt;
Tested-by: Serge Semin &lt;fancer.lancer@gmail.com&gt;
Tested-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Allows relocation exception vectors everywhere</title>
<updated>2024-02-20T11:44:59Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2024-02-16T17:42:12Z</published>
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<id>urn:sha1:5e9d13bd3de8c34ee81b9db8c50887fea5b93834</id>
<content type='text'>
Now the exception vector for CPS systems are allocated on-fly
with memblock as well.

It will try to allocate from KSEG1 first, and then try to allocate
in low 4G if possible.

The main reset vector is now generated by uasm, to avoid tons
of patches to the code. Other vectors are copied to the location
later.

    move 64bits fix in an other patch
    fix cache issue with mips_cps_core_entry
    rewrite the patch to reduce the diff stat
    move extern in header
    use cache address for copying vector

gc: use the new macro CKSEG[0A1]DDR_OR_64BIT()
Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: smp-cps: Don't rely on CP0_CMGCRBASE</title>
<updated>2023-02-27T22:44:57Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2023-02-27T18:46:13Z</published>
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<id>urn:sha1:fea8826d5fdc4ff5c93e883a738597129614039c</id>
<content type='text'>
CP0_CMGCRBASE is not always available on CPS enabled system
such as early proAptiv.

For early SMP bring up where we can't safely access memeory,
we patch the entry of CPS NMI vector to inject CMGCR address
directly into register during early core bringup.

For VPE bringup as the core is already coherenct at that point
we just read the variable to obtain the address.

Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152</title>
<updated>2019-05-30T18:26:32Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-05-27T06:55:01Z</published>
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<id>urn:sha1:2874c5fd284268364ece81a7bd936f3c8168e567</id>
<content type='text'>
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 3029 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>Update MIPS email addresses</title>
<updated>2017-11-03T16:02:30Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@mips.com</email>
</author>
<published>2017-10-26T00:04:33Z</published>
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<id>urn:sha1:fb615d61b5583db92e3793709b97e35dc9499c2a</id>
<content type='text'>
MIPS will soon not be a part of Imagination Technologies, and as such
many @imgtec.com email addresses will no longer be valid. This patch
updates the addresses for those who:

 - Have 10 or more patches in mainline authored using an @imgtec.com
   email address, or any patches dated within the past year.

 - Are still with Imagination but leaving as part of the MIPS business
   unit, as determined from an internal email address list.

 - Haven't already updated their email address (ie. JamesH) or expressed
   a desire to be excluded (ie. Maciej).

 - Acked v2 or earlier of this patch, which leaves Deng-Cheng, Matt &amp;
   myself.

New addresses are of the form firstname.lastname@mips.com, and all
verified against an internal email address list.  An entry is added to
.mailmap for each person such that get_maintainer.pl will report the new
addresses rather than @imgtec.com addresses which will soon be dead.

Instances of the affected addresses throughout the tree are then
mechanically replaced with the new @mips.com address.

Signed-off-by: Paul Burton &lt;paul.burton@mips.com&gt;
Cc: Deng-Cheng Zhu &lt;dengcheng.zhu@imgtec.com&gt;
Cc: Deng-Cheng Zhu &lt;dengcheng.zhu@mips.com&gt;
Acked-by: Dengcheng Zhu &lt;dengcheng.zhu@mips.com&gt;
Cc: Matt Redfearn &lt;matt.redfearn@imgtec.com&gt;
Cc: Matt Redfearn &lt;matt.redfearn@mips.com&gt;
Acked-by: Matt Redfearn &lt;matt.redfearn@mips.com&gt;
Cc: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: trivial@kernel.org
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
</entry>
<entry>
<title>MIPS: smp-cps: Pull boot config retrieval out of mips_cps_boot_vpes</title>
<updated>2016-05-13T12:01:50Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-02-03T03:15:31Z</published>
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<id>urn:sha1:f12401d7219f5a1e361ded834016e5777a10262b</id>
<content type='text'>
The mips_cps_boot_vpes function previously included code to retrieve
pointers to the core &amp; VPE boot configuration structs. These structures
were used both by mips_cps_boot_vpes and by its mips_cps_core_entry
callsite. In preparation for skipping the call to mips_cps_boot_vpes on
some invocations of mips_cps_core_entry, pull the calculation of those
pointers out into a separate function such that it can continue to be
shared.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Cc: Rusty Russell &lt;rusty@rustcorp.com.au&gt;
Cc: Matt Redfearn &lt;matt.redfearn@imgtec.com&gt;
Cc: Niklas Cassel &lt;niklas.cassel@axis.com&gt;
Cc: Ezequiel Garcia &lt;ezequiel.garcia@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12337/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: pm-cps: Prevent use of mips_cps_* without CPS SMP</title>
<updated>2014-07-30T18:47:39Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2014-07-09T11:48:18Z</published>
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<id>urn:sha1:064231e548d0ef90453081f424ced7b3ffffffe9</id>
<content type='text'>
These symbols will not be defined when CONFIG_MIPS_CPS=n, but although
the CPS_PM_POWER_GATED state will never be used in that case the
compiler doesn't have enough information to figure that out. Add checks
which evaluate to a constant false for CONFIG_MIPS_CPS=n cases in order
to help the compiler out &amp; eliminate the symbol references.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Reviewed-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7278/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
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