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<title>kernel/arch/mips/include/asm/r4k-timer.h, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
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<updated>2024-07-03T14:50:12Z</updated>
<entry>
<title>MIPS: sync-r4k: Rework based on x86 tsc_sync</title>
<updated>2024-07-03T14:50:12Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2024-06-12T08:54:32Z</published>
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<id>urn:sha1:580724fce27f2b71b3e4d58bbe6d83b671929b33</id>
<content type='text'>
The original sync-r4k did a good job on reducing jitter by determine
the "next time value", but it has a limitation that when synchronization
being performed too many times due to high core count or CPU hotplug,
the timewrap on CPU0 will become unaccpetable.

Rework the mechanism based on latest x86 tsc_sync. (It seems like
the original implementation is based on tsc_sync at that time,
so it's just a refresh.) To improve overall performance.

Tesed on Loongson64, Boston, QEMU.

Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Correct the header guard of r4k-timer.h</title>
<updated>2020-09-18T13:29:00Z</updated>
<author>
<name>Wei Li</name>
<email>liwei391@huawei.com</email>
</author>
<published>2020-09-18T01:41:11Z</published>
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<id>urn:sha1:38a6445cab6ba4bf6b32f28552d2a7d87dc4414a</id>
<content type='text'>
Rename the header guard of r4k-timer.h from __ASM_R4K_TYPES_H to
__ASM_R4K_TIMER_H what corresponding with the file name.

Signed-off-by: Wei Li &lt;liwei391@huawei.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Synchronize MIPS count one CPU at a time</title>
<updated>2012-08-17T08:57:28Z</updated>
<author>
<name>Jayachandran C</name>
<email>jchandra@broadcom.com</email>
</author>
<published>2012-08-14T13:26:13Z</published>
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<id>urn:sha1:cf9bfe55f24973a8f40e2c922a7e82cf09e486fd</id>
<content type='text'>
The current implementation of synchronise_count_{master,slave} blocks
slave CPUs in early boot until all of them come up. This no longer
works because blocking a CPU with interrupts off after notifying the
CPU to be online causes problems with the current kernel.

Specifically, after the workqueue changes
(commit a08489c569dc1 "Pull workqueue changes from Tejun Heo")
the CPU_ONLINE notification callback workqueue_cpu_up_callback()
will hang on wait_for_completion(&amp;idle_rebind.done), if the slave
CPUs are blocked for synchronize_count_slave().

The changes are to update synchronize_count_{master,slave}() to handle
one CPU at a time and to call synchronise_count_master() in __cpu_up()
so that the CPU_ONLINE notification goes out only after the COP0 COUNT
register is synchronized.

[ralf@linux-mips.org: This matter only to those few platforms which are
using the cp0 counter as their clocksource which are XLP, XLR and MIPS'
CMP solution.]

Signed-off-by: Jayachandran C &lt;jchandra@broadcom.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4216/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Move headfiles to new location below arch/mips/include</title>
<updated>2008-10-11T15:18:52Z</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2008-09-16T17:48:51Z</published>
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<id>urn:sha1:384740dc49ea651ba350704d13ff6be9976e37fe</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
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