<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/arch/mips/include/asm/mipsregs.h, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
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<updated>2025-08-29T20:34:29Z</updated>
<entry>
<title>mips: Replace __ASSEMBLY__ with __ASSEMBLER__ in the mips headers</title>
<updated>2025-08-29T20:34:29Z</updated>
<author>
<name>Thomas Huth</name>
<email>thuth@redhat.com</email>
</author>
<published>2025-08-04T06:56:29Z</published>
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<id>urn:sha1:157f9533f9ffb5d9544515dcfe54e0901d9aa615</id>
<content type='text'>
While the GCC and Clang compilers already define __ASSEMBLER__
automatically when compiling assembler code, __ASSEMBLY__ is a macro
that only gets defined by the Makefiles in the kernel. Defining
such a macro was necessary in the early days of the kernel, since GCC
only started providing __ASSEMBLER__ since version 3.0 in 2000 (see
https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=f8f769ea4e69 ).
However, having two macros can be very confusing nowadays for the
developers when switching between userspace and kernelspace coding,
or when dealing with uapi headers that should use __ASSEMBLER__
instead. So let's now standardize on the __ASSEMBLER__ macro that is
provided by the compilers.

This is almost a completely mechanical patch (done with a simple
"sed -i" statement), with just one comment tweaked manually in
arch/mips/include/asm/cpu.h (that was missing some underscores).

Cc: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
Cc: linux-mips@vger.kernel.org
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Reviewed-by: Maciej W. Rozycki &lt;macro@orcam.me.uk&gt;
Signed-off-by: Thomas Huth &lt;thuth@redhat.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: kernel: Rename read/write_c0_ecc to read/writec0_errctl</title>
<updated>2025-01-11T11:31:21Z</updated>
<author>
<name>Thomas Bogendoerfer</name>
<email>tsbogend@alpha.franken.de</email>
</author>
<published>2024-12-02T15:39:36Z</published>
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<id>urn:sha1:b4fdedd9f045668516291961a71ba7cdfb284907</id>
<content type='text'>
CP0 register 26 is used as ECC register for legacy cores, but newer
cores (MIPS32/MIPS64) use it as an ErrCtl register. Since the kernel only
uses CP0 26 as ErrCtl register rename the access functions to the more
fitting name.

Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
Reviewed-by: Maciej W. Rozycki &lt;macro@orcam.me.uk&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: mipsregs: Parse fp and sp register by name in parse_r</title>
<updated>2024-02-28T11:25:52Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2023-04-09T10:43:06Z</published>
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<id>urn:sha1:af43e871c93640a69af58ddb33aec2d4be80bf6b</id>
<content type='text'>
parse_r helper is used to parse register number from oprand,
it only handles oprand which use number to refer register before.

However compiler may use $gp and $sp to reference register 29 and
30. Handle this situation by adding relevant match name.

Fixes compilation error:
{standard input}: Assembler messages:
{standard input}:1937: Error: Unable to parse register name $fp

Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: mipsregs: Set proper ISA level for virt extensions</title>
<updated>2024-02-23T09:13:48Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2024-02-02T18:21:47Z</published>
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<id>urn:sha1:a640d6762a7d404644201ebf6d2a078e8dc84f97</id>
<content type='text'>
c994a3ec7ecc ("MIPS: set mips32r5 for virt extensions") setted
some instructions in virt extensions to ISA level mips32r5.

However TLB related vz instructions was leftover, also this
shouldn't be done to a R5 or R6 kernel buid.

Reorg macros to set ISA level as needed when _ASM_SET_VIRT
is called.

Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Implement microMIPS MT ASE helpers</title>
<updated>2024-02-23T09:13:47Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2024-02-02T18:21:46Z</published>
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<id>urn:sha1:dd6d29a6148990bb1d39a37c6c2830e6daf9cb46</id>
<content type='text'>
Implement various microMIPS MT ASE helpers accroading to:

MIPS® Architecture for Programmers
Volume IV-f: The MIPS® MT Module for the microMIPS32™ Architecture

Fixes build error:
{standard input}:2616: Error: branch to a symbol in another ISA mode

This make MT ASE available on microMIPS as well.

Boot tested on M5150 with microMIPS enabled on M5150.

Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Unify define of CP0 registers for uasm code</title>
<updated>2024-02-20T11:41:51Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2024-02-09T18:07:47Z</published>
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<id>urn:sha1:a77dabc8e8e4686f542f35e9e3ef09310b018b23</id>
<content type='text'>
Definitions of uasm variant of CP0 registers are unified to
mipsregs.h, so they lay together with uasm variant of
the code.

Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Fix typos</title>
<updated>2024-01-08T09:39:12Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2024-01-03T23:16:03Z</published>
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<id>urn:sha1:2f9060b1db4aa2c21c248e34476d8936a2b69cf6</id>
<content type='text'>
Fix typos, most reported by "codespell arch/mips".  Only touches comments,
no code changes.

Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Cc: linux-mips@vger.kernel.org
Reviewed-by: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Always use -Wa,-msoft-float and eliminate GAS_HAS_SET_HARDFLOAT</title>
<updated>2023-01-26T03:41:16Z</updated>
<author>
<name>Nathan Chancellor</name>
<email>nathan@kernel.org</email>
</author>
<published>2023-01-12T03:04:59Z</published>
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<id>urn:sha1:80a20d2f8288afcd6036bbab8717061806ace4f2</id>
<content type='text'>
-Wa,-msoft-float is tested with as-option, which will be a problem for
clang with an upcoming change to move as-option to use KBUILD_AFLAGS
instead of KBUILD_CFLAGS due to a lack of '-mno-abicalls' in
KBUILD_AFLAGS at the point that this check occurs; $(cflags-y) is added
to KBUILD_AFLAGS towards the end of this file.

  clang: error: ignoring '-fno-PIE' option as it cannot be used with implicit usage of -mabicalls and the N64 ABI [-Werror,-Woption-ignored]

This could be resolved by switching to a cc-option check but
'$(cflags-y)' would need to be added so that '-mno-abicalls' is present
for the test. However, this check is no longer necessary, as
-msoft-float is supported by all supported assembler versions (GNU as
2.25+ and LLVM 11+). Eliminate GAS_HAS_SET_HARDFLOAT and all of its
uses, inlining SET_HARDFLOAT where necessary.

Link: https://lore.kernel.org/202209101939.bvk64Fok-lkp@intel.com/
Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Signed-off-by: Nathan Chancellor &lt;nathan@kernel.org&gt;
Acked-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
Reviewed-by: Nick Desaulniers &lt;ndesaulniers@google.com&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Tested-by: Linux Kernel Functional Testing &lt;lkft@linaro.org&gt;
Tested-by: Anders Roxell &lt;anders.roxell@linaro.org&gt;
Signed-off-by: Masahiro Yamada &lt;masahiroy@kernel.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Remove VR41xx support</title>
<updated>2022-07-14T09:52:29Z</updated>
<author>
<name>Thomas Bogendoerfer</name>
<email>tsbogend@alpha.franken.de</email>
</author>
<published>2022-07-05T16:46:25Z</published>
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<id>urn:sha1:d3164e2f3b0ac003c401d419cda2da0571724352</id>
<content type='text'>
No (active) developer owns this hardware, so let's remove Linux support.

Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: remove asm/war.h</title>
<updated>2022-02-22T08:35:49Z</updated>
<author>
<name>Thomas Bogendoerfer</name>
<email>tsbogend@alpha.franken.de</email>
</author>
<published>2022-02-18T10:04:39Z</published>
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<id>urn:sha1:b56d1cafefaa4550888bace142be404db36b96a1</id>
<content type='text'>
The major part for workaround handling has already moved to config
options. This change replaces the remaining defines by already
available config options and gets rid of war.h

Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
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