<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/arch/mips/include/asm/mach-rc32434, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable'/>
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<updated>2025-03-19T09:22:22Z</updated>
<entry>
<title>MIPS: Fix Macro name</title>
<updated>2025-03-19T09:22:22Z</updated>
<author>
<name>Abhishek Tamboli</name>
<email>abhishektamboli9@gmail.com</email>
</author>
<published>2025-02-27T18:36:28Z</published>
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<id>urn:sha1:ae2b6c6850561926a2a18c3b725b0917f11bc7e6</id>
<content type='text'>
Add missing underscore in PCI_CFGA_BUS macro definition for consistency.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=219744

Signed-off-by: Abhishek Tamboli &lt;abhishektamboli9@gmail.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Fix a compilation issue</title>
<updated>2023-01-27T16:22:06Z</updated>
<author>
<name>xurui</name>
<email>xurui@kylinos.cn</email>
</author>
<published>2023-01-18T08:59:12Z</published>
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<id>urn:sha1:109d587a4b4d7ccca2200ab1f808f43ae23e2585</id>
<content type='text'>
arch/mips/include/asm/mach-rc32434/pci.h:377:
cc1: error: result of ‘-117440512 &lt;&lt; 16’ requires 44 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]

All bits in KORINA_STAT are already at the correct position, so there is
no addtional shift needed.

Signed-off-by: xurui &lt;xurui@kylinos.cn&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: rb532: move GPIOD definition into C-files</title>
<updated>2022-03-30T18:26:26Z</updated>
<author>
<name>Jackie Liu</name>
<email>liuyun01@kylinos.cn</email>
</author>
<published>2022-03-30T12:09:21Z</published>
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<id>urn:sha1:bf64f7fe151b9568443c9b0cf643b3542d36870c</id>
<content type='text'>
My kernel robot reports build error from drivers/iio/adc/da9150-gpadc.c,

  drivers/iio/adc/da9150-gpadc.c:254:13: error: ‘DA9150_GPADC_CHAN_0x08’
  undeclared here (not in a function); did you mean ‘DA9150_GPADC_CHAN_TBAT’?
     254 |  .channel = DA9150_GPADC_CHAN_##_id,

We define GPIOD in rb.h, in fact it should only be used in gpio.c, but
it affects the driver da9150-gpadc.c which goes against the original
intention of the design, just move it to its scope.

Fixes: 1b432840d0a4 ("MIPS: RB532: GPIO register offsets are relative to GPIOBASE")
Suggested-by: Jonathan Cameron &lt;jic23@kernel.org&gt;
Suggested-by: Andy Shevchenko &lt;andy.shevchenko@gmail.com&gt;
Reported-by: k2ci &lt;kernel-bot@kylinos.cn&gt;
Signed-off-by: Jackie Liu &lt;liuyun01@kylinos.cn&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Remove TX39XX support</title>
<updated>2022-03-01T09:07:22Z</updated>
<author>
<name>Thomas Bogendoerfer</name>
<email>tsbogend@alpha.franken.de</email>
</author>
<published>2022-02-22T09:04:28Z</published>
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<id>urn:sha1:455481fc9a807798eca05f6fb0918ab88109d845</id>
<content type='text'>
No (active) developer owns this hardware, so let's remove Linux support.

Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
Acked-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Reviewed-by: Geert Uytterhoeven &lt;geert@linux-m68k.org&gt;
Tested-by: Geert Uytterhoeven &lt;geert@linux-m68k.org&gt;
Acked-by: Atsushi Nemoto &lt;anemo@mba.ocn.ne.jp&gt;
</content>
</entry>
<entry>
<title>MIPS: don't include &lt;linux/genhd.h&gt; in &lt;asm/mach-rc32434/rb.h&gt;</title>
<updated>2021-08-02T19:37:27Z</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2021-07-27T05:56:32Z</published>
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<id>urn:sha1:4c7251e1b576d884046e62d23505e75486f88c1f</id>
<content type='text'>
There is no need to include genhd.h from a random arch header, and not
doing so prevents the possibility for nasty include loops.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Chaitanya Kulkarni &lt;chaitanya.kulkarni@wdc.com&gt;
Reviewed-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
Reviewed-by: Ira Weiny &lt;ira.weiny@intel.com&gt;
Link: https://lore.kernel.org/r/20210727055646.118787-2-hch@lst.de
Signed-off-by: Jens Axboe &lt;axboe@kernel.dk&gt;
</content>
</entry>
<entry>
<title>MIPS: Remove mach-*/war.h</title>
<updated>2020-09-07T20:25:27Z</updated>
<author>
<name>Thomas Bogendoerfer</name>
<email>tsbogend@alpha.franken.de</email>
</author>
<published>2020-08-24T16:32:54Z</published>
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<id>urn:sha1:601637e42df045ca2d1a9324d56765f044d46866</id>
<content type='text'>
After conversion of all WAR defines we can now remove all mach-*/war.h
files.

Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Get rid of BCM1250_M3_WAR</title>
<updated>2020-09-07T20:25:03Z</updated>
<author>
<name>Thomas Bogendoerfer</name>
<email>tsbogend@alpha.franken.de</email>
</author>
<published>2020-08-24T16:32:52Z</published>
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<id>urn:sha1:ab5743079b8e3d3d4309664903f6b1f579168a56</id>
<content type='text'>
BCM1250_M3_WAR is depending on CONFIG_CONFIG_SB1_PASS_2_WORKAROUNDS.
So using this option directly lets and remove define.

Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS</title>
<updated>2020-09-07T20:24:51Z</updated>
<author>
<name>Thomas Bogendoerfer</name>
<email>tsbogend@alpha.franken.de</email>
</author>
<published>2020-08-24T16:32:51Z</published>
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<id>urn:sha1:43df4eb2fc9511e09c66252c3fec4f8933a77c73</id>
<content type='text'>
SB1250 uart bug is related to PASS 2 workarounds. Use config
CONFIG_SB1_PASS_2_WORKAROUNDS directly and get rid of SIBYTE_1956_WAR.

Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option</title>
<updated>2020-09-07T20:24:40Z</updated>
<author>
<name>Thomas Bogendoerfer</name>
<email>tsbogend@alpha.franken.de</email>
</author>
<published>2020-08-24T16:32:50Z</published>
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<id>urn:sha1:a7fbed988f31d3bf92415226fdf2ffd54606ad93</id>
<content type='text'>
Use a new config option to enable MIPS 34K ITLB workaround and remove
define from different war.h files.

Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Convert R10000_LLSC_WAR info a config option</title>
<updated>2020-09-07T20:24:27Z</updated>
<author>
<name>Thomas Bogendoerfer</name>
<email>tsbogend@alpha.franken.de</email>
</author>
<published>2020-08-24T16:32:49Z</published>
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<id>urn:sha1:256ec489f1c7726f0db9ffee88ba7cdc317806cd</id>
<content type='text'>
Use a new config option to enabel R1000_LLSC workaound and remove
define from different war.h files.

Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
</feed>
