<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/arch/mips/boot/dts/mscc, branch linux-6.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y</id>
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<updated>2022-12-08T10:34:03Z</updated>
<entry>
<title>MIPS: mscc: jaguar2: Fix pca9545 i2c-mux node names</title>
<updated>2022-12-08T10:34:03Z</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2022-12-02T16:49:25Z</published>
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<id>urn:sha1:f5739014669a734e42af9e73deb1ca165f49b5ae</id>
<content type='text'>
"make dtbs_check":

    arch/mips/boot/dts/mscc/jaguar2_pcb110.dtb: pca9545@70: $nodename:0: 'pca9545@70' does not match '^(i2c-?)?mux'
	    From schema: Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml
    arch/mips/boot/dts/mscc/jaguar2_pcb110.dtb: pca9545@70: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'i2c@0', 'i2c@1', 'i2c@2', 'i2c@3' were unexpected)
	    From schema: Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml
    ...

Fix this by renaming PCA9545 nodes to "i2c-mux", to match the I2C bus
multiplexer/switch DT bindings and the Generic Names Recommendation in
the Devicetree Specification.

Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: mscc: ocelot: enable FDMA usage</title>
<updated>2022-07-05T09:12:30Z</updated>
<author>
<name>Alexandre Belloni</name>
<email>alexandre.belloni@bootlin.com</email>
</author>
<published>2022-06-24T15:25:48Z</published>
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<id>urn:sha1:5f7e2f3e7ce78719c438e9240ea7aa6779632068</id>
<content type='text'>
Enable FDMA usage by adding "fdma" resource in regs and interrupts.

Signed-off-by: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Signed-off-by: Clément Léger &lt;clement.leger@bootlin.com&gt;
Reviewed-by: Vladimir Oltean &lt;vladimir.oltean@nxp.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: mscc: serval: rename pinctrl nodes</title>
<updated>2022-04-27T08:48:59Z</updated>
<author>
<name>Michael Walle</name>
<email>michael@walle.cc</email>
</author>
<published>2022-04-20T19:50:18Z</published>
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<id>urn:sha1:860f39bea3194ee227e0937dd0ebf1e53cc21cc1</id>
<content type='text'>
The pinctrl device tree binding will be converted to YAML format. Rename
the pin nodes so they end with "-pins" to match the schema.

Signed-off-by: Michael Walle &lt;michael@walle.cc&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: mscc: ocelot: rename pinctrl nodes</title>
<updated>2022-04-27T08:48:59Z</updated>
<author>
<name>Michael Walle</name>
<email>michael@walle.cc</email>
</author>
<published>2022-04-20T19:50:17Z</published>
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<id>urn:sha1:ee5930c99a193481edee56c09ef8b71a06a242e6</id>
<content type='text'>
The pinctrl device tree binding will be converted to YAML format. Rename
the pin nodes so they end with "-pins" to match the schema.

Signed-off-by: Michael Walle &lt;michael@walle.cc&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: mscc: jaguar2: rename pinctrl nodes</title>
<updated>2022-04-27T08:48:59Z</updated>
<author>
<name>Michael Walle</name>
<email>michael@walle.cc</email>
</author>
<published>2022-04-20T19:50:16Z</published>
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<id>urn:sha1:3949aaa608f37f93d9648e4c68f1c113269dac53</id>
<content type='text'>
The pinctrl device tree binding will be converted to YAML format. Rename
the pin nodes so they end with "-pins" to match the schema.

Signed-off-by: Michael Walle &lt;michael@walle.cc&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: mscc: ocelot: mark the phy-mode for internal PHY ports</title>
<updated>2021-08-21T08:38:48Z</updated>
<author>
<name>Vladimir Oltean</name>
<email>vladimir.oltean@nxp.com</email>
</author>
<published>2021-08-19T17:04:16Z</published>
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<id>urn:sha1:eba54cbb92d28b4f6dc1ed5f73f5187b09d82c08</id>
<content type='text'>
The ocelot driver was converted to phylink, and that expects a valid
phy_interface_t. Without a phy-mode, of_get_phy_mode returns
PHY_INTERFACE_MODE_NA, which is not ideal because phylink rejects that.

The ocelot driver was patched to treat PHY_INTERFACE_MODE_NA as
PHY_INTERFACE_MODE_INTERNAL to work with the broken DT blobs, but we
should fix the device trees and specify the phy-mode too.

Signed-off-by: Vladimir Oltean &lt;vladimir.oltean@nxp.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: mscc: ocelot: disable all switch ports by default</title>
<updated>2021-08-21T08:38:29Z</updated>
<author>
<name>Vladimir Oltean</name>
<email>vladimir.oltean@nxp.com</email>
</author>
<published>2021-08-19T17:04:15Z</published>
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<id>urn:sha1:0181f6f19c6c35b24f1516d8db22f3bbce762633</id>
<content type='text'>
The ocelot switch driver used to ignore ports which do not have a
phy-handle property and not probe those, but this is not quite ok since
it is valid to not have a phy-handle property if there is a fixed-link.

It seems that checking for a phy-handle was a proxy for the proper check
which is for the status, but that doesn't make a lot of sense, since the
ocelot driver already iterates using for_each_available_child_of_node
which skips the disabled ports, so I have no idea.

Anyway, a widespread pattern in device trees is for a SoC dtsi to
disable by default all hardware, and let board dts files enable what is
used. So let's do that and enable only the ports with a phy-handle in
the pcb120 and pcb123 device tree files.

Signed-off-by: Vladimir Oltean &lt;vladimir.oltean@nxp.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: mscc: Add serval support</title>
<updated>2020-11-12T22:35:15Z</updated>
<author>
<name>Gregory CLEMENT</name>
<email>gregory.clement@bootlin.com</email>
</author>
<published>2020-11-10T11:45:08Z</published>
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<id>urn:sha1:fe0052018a84d50be034449b4175177f569fbf5c</id>
<content type='text'>
Add a device trees and FIT image support for the Microsemi Serval SoC
which belongs to same family of the Ocelot SoC.

It is based on the work of Lars Povlsen &lt;lars.povlsen@microchip.com&gt;.

Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
Acked-by: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: mscc: Add jaguar2 support</title>
<updated>2020-11-12T22:34:25Z</updated>
<author>
<name>Gregory CLEMENT</name>
<email>gregory.clement@bootlin.com</email>
</author>
<published>2020-11-10T11:45:07Z</published>
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<id>urn:sha1:f84778f7d8c3b867d6aaca9361d7b43b222f9f6a</id>
<content type='text'>
Add a device trees and FIT image support for the Microsemi Jaguar2 SoC
which belongs to same family of the Ocelot SoC.

It is based on the work of Lars Povlsen &lt;lars.povlsen@microchip.com&gt;.

Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
Acked-by: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: mscc: Add luton PC0B91 device tree</title>
<updated>2020-11-12T22:33:42Z</updated>
<author>
<name>Gregory CLEMENT</name>
<email>gregory.clement@bootlin.com</email>
</author>
<published>2020-11-10T11:45:05Z</published>
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<id>urn:sha1:72bc5e8b25a0031354a27c1da2b89104e2bf32e3</id>
<content type='text'>
Add a device tree for the Microsemi Luton PCB091 evaluation board.

It is based on the work of Lars Povlsen &lt;lars.povlsen@microchip.com&gt;.

Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
Acked-by: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
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