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<title>kernel/arch/csky/include/asm/tlb.h, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
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<updated>2022-07-21T17:50:13Z</updated>
<entry>
<title>csky/tlb: Remove tlb_flush() define</title>
<updated>2022-07-21T17:50:13Z</updated>
<author>
<name>Peter Zijlstra</name>
<email>peterz@infradead.org</email>
</author>
<published>2022-07-08T07:18:04Z</published>
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<id>urn:sha1:1d7708e75c49d08392884a08feeebaa3f9d80703</id>
<content type='text'>
The previous patch removed the tlb_flush_end() implementation which
used tlb_flush_range(). This means:

 - csky did double invalidates, a range invalidate per vma and a full
   invalidate at the end

 - csky actually has range invalidates and as such the generic
   tlb_flush implementation is more efficient for it.

Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Acked-by: Will Deacon &lt;will@kernel.org&gt;
Tested-by: Guo Ren &lt;guoren@kernel.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
</entry>
<entry>
<title>mmu_gather: Remove per arch tlb_{start,end}_vma()</title>
<updated>2022-07-21T17:50:13Z</updated>
<author>
<name>Peter Zijlstra</name>
<email>peterz@infradead.org</email>
</author>
<published>2022-07-08T07:18:03Z</published>
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<id>urn:sha1:1e9fdf21a4339b102539f476a9842e7526c01939</id>
<content type='text'>
Scattered across the archs are 3 basic forms of tlb_{start,end}_vma().
Provide two new MMU_GATHER_knobs to enumerate them and remove the per
arch tlb_{start,end}_vma() implementations.

 - MMU_GATHER_NO_FLUSH_CACHE indicates the arch has flush_cache_range()
   but does *NOT* want to call it for each VMA.

 - MMU_GATHER_MERGE_VMAS indicates the arch wants to merge the
   invalidate across multiple VMAs if possible.

With these it is possible to capture the three forms:

  1) empty stubs;
     select MMU_GATHER_NO_FLUSH_CACHE and MMU_GATHER_MERGE_VMAS

  2) start: flush_cache_range(), end: empty;
     select MMU_GATHER_MERGE_VMAS

  3) start: flush_cache_range(), end: flush_tlb_range();
     default

Obviously, if the architecture does not have flush_cache_range() then
it also doesn't need to select MMU_GATHER_NO_FLUSH_CACHE.

Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Acked-by: Will Deacon &lt;will@kernel.org&gt;
Cc: David Miller &lt;davem@davemloft.net&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
</entry>
<entry>
<title>csky: Fixup compile error</title>
<updated>2021-02-27T14:04:14Z</updated>
<author>
<name>Guo Ren</name>
<email>guoren@linux.alibaba.com</email>
</author>
<published>2021-02-27T14:00:35Z</published>
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<id>urn:sha1:6607aa6f6b68fc9b5955755f1b1be125cf2a9d03</id>
<content type='text'>
: error: C++ style comments are not allowed in ISO C90
 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
 ^
error: (this will be reported only once per input file)

Signed-off-by: Guo Ren &lt;guoren@linux.alibaba.com&gt;
</content>
</entry>
<entry>
<title>csky: add missing brackets in a macro for tlb.h</title>
<updated>2019-09-07T07:28:05Z</updated>
<author>
<name>Jason Gunthorpe</name>
<email>jgg@mellanox.com</email>
</author>
<published>2019-09-02T05:47:05Z</published>
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<id>urn:sha1:6bdf3b0aeead8edf91306dd60dcf676c257aad30</id>
<content type='text'>
As an earlier patch made the macro argument more complicated, compilation
now fails with:

 In file included from mm/madvise.c:30:
 mm/madvise.c: In function 'madvise_free_single_vma':
 arch/csky/include/asm/tlb.h:11:11: error:
     invalid type argument of '-&gt;' (have 'struct mmu_gather')

Link: https://lore.kernel.org/r/20190901193601.GB5208@mellanox.com
Fixes: 923bfc561e75 ("pagewalk: separate function pointers from iterator data")
Reported-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@mellanox.com&gt;
</content>
</entry>
<entry>
<title>csky: Cache and TLB routines</title>
<updated>2018-10-25T15:36:19Z</updated>
<author>
<name>Guo Ren</name>
<email>ren_guo@c-sky.com</email>
</author>
<published>2018-09-05T06:25:10Z</published>
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<id>urn:sha1:00a9730e1007c6cc87a7c78af2f24a4105d616ee</id>
<content type='text'>
This patch adds cache and tlb sync codes for abiv1 &amp; abiv2.

Signed-off-by: Guo Ren &lt;ren_guo@c-sky.com&gt;
Reviewed-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
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