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<title>kernel/arch/csky/include/asm/pgtable.h, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y'/>
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<updated>2019-02-13T01:48:14Z</updated>
<entry>
<title>csky: Fixup io-range page attribute for mmap("/dev/mem")</title>
<updated>2019-02-13T01:48:14Z</updated>
<author>
<name>Guo Ren</name>
<email>ren_guo@c-sky.com</email>
</author>
<published>2019-01-30T12:13:11Z</published>
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<id>urn:sha1:76d21d186a65523b08ea5f70302e2c29ee8f6a8d</id>
<content type='text'>
Some user space drivers need accessing IO address and IO remap need
SO(strong order) page-attribute to make IO operation correct. So we
need add SO-page-attr for all non-memory address.

Signed-off-by: Guo Ren &lt;ren_guo@c-sky.com&gt;
Reported-by: Fan Xiaodong &lt;xiaodong.fan@boyahualu.com&gt;
</content>
</entry>
<entry>
<title>csky: Fixup _PAGE_GLOBAL bit for 610 tlb entry</title>
<updated>2019-02-13T01:48:14Z</updated>
<author>
<name>Guo Ren</name>
<email>ren_guo@c-sky.com</email>
</author>
<published>2019-01-11T04:48:25Z</published>
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<id>urn:sha1:62eebea655d4be5a20fd563abfd7656724cdcd00</id>
<content type='text'>
C-SKY CPU 8xx's _PAGE_GLOBAL is BIT(0), but 610's _PAGE_GLOBAL is
BIT(6). Use _PAGE_GLOBAL macro instead of bad magic number.

Signed-off-by: Guo Ren &lt;ren_guo@c-sky.com&gt;
</content>
</entry>
<entry>
<title>csky: MMU and page table management</title>
<updated>2018-10-25T15:36:19Z</updated>
<author>
<name>Guo Ren</name>
<email>ren_guo@c-sky.com</email>
</author>
<published>2018-09-05T06:25:12Z</published>
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<id>urn:sha1:013de2d6671d89de3397904749c86a69ac0686f7</id>
<content type='text'>
This patch adds files related to memory management and here is our
memory-layout:

   Fixmap       : 0xffc02000 – 0xfffff000       (4 MB - 12KB)
   Pkmap        : 0xff800000 – 0xffc00000       (4 MB)
   Vmalloc      : 0xf0200000 – 0xff000000       (238 MB)
   Lowmem       : 0x80000000 – 0xc0000000       (1GB)

abiv1 CPU (CK610) is VIPT cache and it doesn't support highmem.
abiv2 CPUs are all PIPT cache and they could support highmem.

Lowmem is directly mapped by msa0 &amp; msa1 reg, and we needn't setup
memory page table for it.

Link:https://lore.kernel.org/lkml/20180518215548.GH17671@n2100.armlinux.org.uk/
Signed-off-by: Guo Ren &lt;ren_guo@c-sky.com&gt;
Cc: Christoph Hellwig &lt;hch@infradead.org&gt;
Reviewed-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
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