kernel/arch/csky/include/asm/mmu_context.h, branch linux-rolling-stable

csky: Fixup compile error

2021-02-27T14:04:14Z

csky: Fix TLB maintenance synchronization problem

2021-01-12T01:52:41Z

TLB invalidate didn't contain a barrier operation in csky cpu and we need to prevent previous PTW response after TLB invalidation instruction. Of cause, the ASID changing also needs to take care of the issue. CPU0 CPU1 =============== =============== set_pte sync_is() -> See the previous set_pte for all harts tlbi.vas -> Invalidate all harts TLB entry & flush pipeline Signed-off-by: Guo Ren

csky: Add memory layout 2.5G(user):1.5G(kernel)

2021-01-12T01:52:40Z

There are two ways for translating va to pa for csky: - Use TLB(Translate Lookup Buffer) and PTW (Page Table Walk) - Use SSEG0/1 (Simple Segment Mapping) We use tlb mapping 0-2G and 3G-4G virtual address area and SSEG0/1 are for 2G-2.5G and 2.5G-3G translation. We could disable SSEG0 to use 2G-2.5G as TLB user mapping. Signed-off-by: Guo Ren

csky: use asm-generic/mmu_context.h for no-op implementations

2020-10-27T15:02:34Z

Signed-off-by: Nicholas Piggin Acked-by: Guo Ren Cc: linux-csky@vger.kernel.org Signed-off-by: Arnd Bergmann

csky: Add flush_icache_mm to defer flush icache all

2020-02-21T07:43:24Z

Some CPUs don't support icache.va instruction to maintain the whole smp cores' icache. Using icache.all + IPI casue a lot on performace and using defer mechanism could reduce the number of calling icache _flush_all functions. Signed-off-by: Guo Ren

csky: Use generic asid algorithm to implement switch_mm

2019-07-19T06:21:36Z

Use linux generic asid/vmid algorithm to implement csky switch_mm function. The algorithm is from arm and it could work with SMP system. It'll help reduce tlb flush for switch_mm in task/vm switch. Signed-off-by: Guo Ren Cc: Arnd Bergmann

csky: Revert mmu ASID mechanism

2019-07-19T06:21:36Z

Current C-SKY ASID mechanism is from mips and it doesn't work well with multi-cores. ASID per core mechanism is not suitable for C-SKY SMP tlb maintain operations, eg: tlbi.vas need share the same asid in all processors and it'll invalid the tlb entry in all cores with the same asid. This patch is prepare for new ASID mechanism. Signed-off-by: Guo Ren Cc: Arnd Bergmann

csky: Use va_pa_offset instead of phys_offset

2019-04-22T05:44:57Z

The name of phys_offset is so common for global export and it may conflict with some local name. So change phys_offset to va_pa_offset which also used by riscv. Also use __pa() and __va() instead of using phys_offset directly. Signed-off-by: Guo Ren Cc: Arnd Bergmann

csky: Support dynamic start physical address

2019-04-22T05:44:57Z

Before this patch csky-linux need CONFIG_RAM_BASE to determine start physical address. Now we use phys_offset variable to replace the macro of PHYS_OFFSET and we setup phys_offset with real physical address which is determined during startup in head.S. With this patch we needn't re-compile kernel for different start physical address. ie: 0x0 / 0xc0000000 start physical address could use the same vmlinux, be care different start address must be 512MB aligned. Signed-off-by: Guo Ren Cc: Arnd Bergmann

csky: bugfix tlb_get_pgd error.

2018-12-03T02:49:11Z

It's wrong to mask/unmask highest bit in addr to translate the vaddr to paddr. We should use PAGE_OFFSET and PHYS_OFFSET. Wrong implement: return ((get_pgd()|(1<<31)) - PHYS_OFFSET) & ~1; When PHYS_OFFSET=0xc0000000 and get_pgd() return 0xe0000000, it'll return 0x60000000. It's wrong and should be 0xa0000000. Now correct it to: return ((get_pgd() - PHYS_OFFSET) & ~1) + PAGE_OFFSET; Signed-off-by: Guo Ren