kernel/arch/csky/include/asm/cmpxchg.h, branch linux-rolling-stable

csky: Emulate one-byte cmpxchg

2024-05-11T14:07:07Z

Use the new cmpxchg_emu_u8() to emulate one-byte cmpxchg() on csky. [ paulmck: Apply kernel test robot feedback. ] [ paulmck: Drop two-byte support per Arnd Bergmann feedback. ] Co-developed-by: Yujie Liu Signed-off-by: Yujie Liu Signed-off-by: Paul E. McKenney Tested-by: Yujie Liu Reviewed-by: Guo Ren Cc: Arnd Bergmann Cc:

csky: cmpxchg: Coding convention for BUILD_BUG()

2022-08-01T01:57:30Z

Use BUILD_BUG() instead of the custom bad_xchg. Signed-off-by: Guo Ren Signed-off-by: Guo Ren

csky: Add qspinlock support

2022-07-31T09:24:42Z

Enable qspinlock by the requirements mentioned in a8ad07e5240c9 ("asm-generic: qspinlock: Indicate the use of mixed-size atomics"). C-SKY only has "ldex/stex" for all atomic operations. So csky give a strong forward guarantee for "ldex/stex." That means when ldex grabbed the cache line into $L1, it would block other cores from snooping the address with several cycles. The atomic_fetch_add & xchg16 has the same forward guarantee level in C-SKY. Qspinlock has better code size and performance in a fast path. Signed-off-by: Guo Ren Signed-off-by: Guo Ren

csky: atomic: Optimize cmpxchg with acquire & release

2022-04-25T05:51:42Z

Optimize cmpxchg with ASM acquire/release fence ASM instructions instead of previous generic based. Prevent a fence when cmxchg's first load != old. Comments by Rutland: 8e86f0b409a4 ("arm64: atomics: fix use of acquire + release for full barrier semantics") Comments by Boqun: FWIW, you probably need to make sure that a barrier instruction inside an lr/sc loop is a good thing. IIUC, the execution time of a barrier instruction is determined by the status of store buffers and invalidate queues (and probably other stuffs), so it may increase the execution time of the lr/sc loop, and make it unlikely to succeed. But this really depends on how the arch executes these instructions. Link: https://lore.kernel.org/linux-riscv/CAJF2gTSAxpAi=LbAdu7jntZRUa=-dJwL0VfmDfBV5MHB=rcZ-w@mail.gmail.com/T/#m27a0f1342995deae49ce1d0e1f2683f8a181d6c3 Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Mark Rutland

locking/atomic: csky: move to ARCH_ATOMIC

2021-05-26T11:20:51Z

We'd like all architectures to convert to ARCH_ATOMIC, as once all architectures are converted it will be possible to make significant cleanups to the atomics headers, and this will make it much easier to generically enable atomic functionality (e.g. debug logic in the instrumented wrappers). As a step towards that, this patch migrates csky to ARCH_ATOMIC. The arch code provides arch_{atomic,atomic64,xchg,cmpxchg}*(), and common code wraps these with optional instrumentation to provide the regular functions. Signed-off-by: Mark Rutland Acked-by: Guo Ren Cc: Boqun Feng Cc: Peter Zijlstra Cc: Will Deacon Signed-off-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/20210525140232.53872-17-mark.rutland@arm.com

csky: Fixup asm/cmpxchg.h with correct ordering barrier

2021-01-12T01:52:40Z

Optimize the performance of cmpxchg by using more fine-grained acquire/release barriers. Signed-off-by: Guo Ren Cc: Peter Zijlstra Cc: Arnd Bergmann Cc: Paul E. McKenney

csky: Atomic operations

2018-10-25T16:54:23Z

This patch adds atomic, cmpxchg, spinlock files. Signed-off-by: Guo Ren Cc: Andrea Parri Cc: Arnd Bergmann Reviewed-by: Peter Zijlstra