kernel/arch/blackfin/include/asm/cacheflush.h, branch linux-rolling-stable

arch: remove blackfin port

2018-03-16T09:55:47Z

The Analog Devices Blackfin port was added in 2007 and was rather active for a while, but all work on it has come to a standstill over time, as Analog have changed their product line-up. Aaron Wu confirmed that the architecture port is no longer relevant, and multiple people suggested removing blackfin independently because of some of its oddities like a non-working SMP port, and the amount of duplication between the chip variants, which cause extra work when doing cross-architecture changes. Link: https://docs.blackfin.uclinux.org/ Acked-by: Aaron Wu Acked-by: Bryan Wu Cc: Steven Miao Cc: Mike Frysinger Signed-off-by: Arnd Bergmann

Blackfin: don't attempt to flush on-chip L1 SRAM regions

2011-05-25T12:13:41Z

Since the on-chip L1 regions are not cacheable, there is no point in trying to flush/invalidate them. Plus, older Blackfin parts like to trigger an exception (like BF533-0.3). Signed-off-by: Sonic Zhang Signed-off-by: Mike Frysinger

Blackfin: SMP: rename the arch_xxx lock funcs to __raw_xxx

2011-01-10T12:18:11Z

The external functions are named __raw_xxx, not arch_xxx, so rename the prototypes to match reality. This fixes some simple build errors in the bfin_ksyms.c code which exports these helpers to modules. Signed-off-by: Graf Yang Signed-off-by: Mike Frysinger

Blackfin: push down asm/ includes and out of bfin-global.h

2009-12-15T05:14:14Z

Avoid including unnecessary headers all the time as well as circular includes with core requirements. Signed-off-by: Mike Frysinger

block: add helpers to run flush_dcache_page() against a bio and a request's pages

2009-11-26T08:16:19Z

Mtdblock driver doesn't call flush_dcache_page for pages in request. So, this causes problems on architectures where the icache doesn't fill from the dcache or with dcache aliases. The patch fixes this. The ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE symbol was introduced to avoid pointless empty cache-thrashing loops on architectures for which flush_dcache_page() is a no-op. Every architecture was provided with this flush pages on architectires where ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE is equal 1 or do nothing otherwise. See "fix mtd_blkdevs problem with caches on some architectures" discussion on LKML for more information. Signed-off-by: Ilya Loginov Cc: Ingo Molnar Cc: David Woodhouse Cc: Peter Horton Cc: "Ed L. Cashin" Signed-off-by: Jens Axboe

Blackfin: mass clean up of copyright/licensing info

2009-10-07T08:36:26Z

Bill Gatliff & David Brownell pointed out we were missing some copyrights, and licensing terms in some of the files in ./arch/blackfin, so this fixes things, and cleans them up. It also removes: - verbose GPL text(refer to the top level ./COPYING file) - file names (you are looking at the file) - bug url (it's in the ./MAINTAINERS file) - "or later" on GPL-2, when we did not have that right It also allows some Blackfin-specific assembly files to be under a BSD like license (for people to use them outside of Linux). Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger

Blackfin: decouple unrelated cache settings to get exact behavior

2009-06-23T01:15:59Z

The current cache options don't really represent the hardware features. They end up setting different aspects of the hardware so that the end result is to turn on/off the cache. Unfortunately, when we hit cache problems with the hardware, it's difficult to test different settings to root cause the problem. The current settings also don't cleanly allow for different caching behaviors with different regions of memory. So split the configure options such that they properly reflect the settings that are applied to the hardware. Signed-off-by: Jie Zhang Signed-off-by: Mike Frysinger

Blackfin: add blackfin_invalidate_entire_icache for SMP systems

2009-06-13T11:20:07Z

The KGDB code uses this when switching processors to make sure the icache is in a valid state. Signed-off-by: Sonic Zhang Signed-off-by: Mike Frysinger

Blackfin: rename bfin_addr_dcachable to bfin_addr_dcacheable

2009-06-13T11:20:06Z

The latter naming convention is much more common. Signed-off-by: Jie Zhang Signed-off-by: Mike Frysinger

Blackfin: fix detection of cached L2 SRAM

2009-06-12T10:11:25Z

Make sure our bfin_addr_dcachable() function flags cached L2 SRAM properly else memory easily goes unflushed when working with DMA. Signed-off-by: Mike Frysinger