<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/arch/arm64/kvm/hyp/nvhe/debug-sr.c, branch linux-6.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y'/>
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<updated>2022-06-29T09:23:03Z</updated>
<entry>
<title>KVM: arm64: Move vcpu debug/SPE/TRBE flags to the input flag set</title>
<updated>2022-06-29T09:23:03Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2022-05-28T11:38:19Z</published>
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<id>urn:sha1:b1da49088ac68a21c613efd734dada8272ec0b00</id>
<content type='text'>
The three debug flags (which deal with the debug registers, SPE and
TRBE) all are input flags to the hypervisor code.

Move them into the input set and convert them to the new accessors.

Reviewed-by: Fuad Tabba &lt;tabba@google.com&gt;
Reviewed-by: Reiji Watanabe &lt;reijiw@google.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
</content>
</entry>
<entry>
<title>KVM: arm64: MDCR_EL2 is a 64-bit register</title>
<updated>2021-08-20T10:12:17Z</updated>
<author>
<name>Fuad Tabba</name>
<email>tabba@google.com</email>
</author>
<published>2021-08-17T08:11:22Z</published>
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<id>urn:sha1:d6c850dd6ce9ce4b410142a600d8c34dc041d860</id>
<content type='text'>
Fix the places in KVM that treat MDCR_EL2 as a 32-bit register.
More recent features (e.g., FEAT_SPEv1p2) use bits above 31.

No functional change intended.

Acked-by: Will Deacon &lt;will@kernel.org&gt;
Signed-off-by: Fuad Tabba &lt;tabba@google.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20210817081134.2918285-4-tabba@google.com
</content>
</entry>
<entry>
<title>arm64: KVM: Enable access to TRBE support for host</title>
<updated>2021-04-06T22:05:28Z</updated>
<author>
<name>Suzuki K Poulose</name>
<email>suzuki.poulose@arm.com</email>
</author>
<published>2021-04-05T16:42:54Z</published>
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<id>urn:sha1:a1319260bf62951e279ea228f682bf4b8834a3c2</id>
<content type='text'>
For a nvhe host, the EL2 must allow the EL1&amp;0 translation
regime for TraceBuffer (MDCR_EL2.E2TB == 0b11). This must
be saved/restored over a trip to the guest. Also, before
entering the guest, we must flush any trace data if the
TRBE was enabled. And we must prohibit the generation
of trace while we are in EL1 by clearing the TRFCR_EL1.

For vhe, the EL2 must prevent the EL1 access to the Trace
Buffer.

The MDCR_EL2 bit definitions for TRBE are available here :

  https://developer.arm.com/documentation/ddi0601/2020-12/AArch64-Registers/

Cc: Will Deacon &lt;will@kernel.org&gt;
Cc: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Cc: Marc Zyngier &lt;maz@kernel.org&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: Anshuman Khandual &lt;anshuman.khandual@arm.com&gt;
Signed-off-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Acked-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20210405164307.1720226-8-suzuki.poulose@arm.com
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
</content>
</entry>
<entry>
<title>KVM: arm64: Move SPE availability check to VCPU load</title>
<updated>2021-04-06T22:05:20Z</updated>
<author>
<name>Suzuki K Poulose</name>
<email>suzuki.poulose@arm.com</email>
</author>
<published>2021-04-05T16:42:53Z</published>
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<id>urn:sha1:d2602bb4f5a450642b96d467e27e6d5d3ef7fa54</id>
<content type='text'>
At the moment, we check the availability of SPE on the given
CPU (i.e, SPE is implemented and is allowed at the host) during
every guest entry. This can be optimized a bit by moving the
check to vcpu_load time and recording the availability of the
feature on the current CPU via a new flag. This will also be useful
for adding the TRBE support.

Cc: Marc Zyngier &lt;maz@kernel.org&gt;
Cc: Will Deacon &lt;will@kernel.org&gt;
Cc: Alexandru Elisei &lt;Alexandru.Elisei@arm.com&gt;
Cc: James Morse &lt;james.morse@arm.com&gt;
Signed-off-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Acked-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20210405164307.1720226-7-suzuki.poulose@arm.com
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
</content>
</entry>
<entry>
<title>KVM: arm64: nvhe: Save the SPE context early</title>
<updated>2021-03-06T09:18:39Z</updated>
<author>
<name>Suzuki K Poulose</name>
<email>suzuki.poulose@arm.com</email>
</author>
<published>2021-03-05T18:52:47Z</published>
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<id>urn:sha1:b96b0c5de685df82019e16826a282d53d86d112c</id>
<content type='text'>
The nVHE KVM hyp drains and disables the SPE buffer, before
entering the guest, as the EL1&amp;0 translation regime
is going to be loaded with that of the guest.

But this operation is performed way too late, because :
  - The owning translation regime of the SPE buffer
    is transferred to EL2. (MDCR_EL2_E2PB == 0)
  - The guest Stage1 is loaded.

Thus the flush could use the host EL1 virtual address,
but use the EL2 translations instead of host EL1, for writing
out any cached data.

Fix this by moving the SPE buffer handling early enough.
The restore path is doing the right thing.

Fixes: 014c4c77aad7 ("KVM: arm64: Improve debug register save/restore flow")
Cc: stable@vger.kernel.org
Cc: Christoffer Dall &lt;christoffer.dall@arm.com&gt;
Cc: Marc Zyngier &lt;maz@kernel.org&gt;
Cc: Will Deacon &lt;will@kernel.org&gt;
Cc: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: Alexandru Elisei &lt;alexandru.elisei@arm.com&gt;
Reviewed-by: Alexandru Elisei &lt;alexandru.elisei@arm.com&gt;
Signed-off-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20210302120345.3102874-1-suzuki.poulose@arm.com
Message-Id: &lt;20210305185254.3730990-2-maz@kernel.org&gt;
Signed-off-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
</content>
</entry>
<entry>
<title>KVM: arm64: Remove __hyp_text macro, use build rules instead</title>
<updated>2020-07-05T17:38:45Z</updated>
<author>
<name>David Brazdil</name>
<email>dbrazdil@google.com</email>
</author>
<published>2020-06-25T13:14:19Z</published>
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<id>urn:sha1:c50cb04303cb88c517715b078e3e010c024af1a5</id>
<content type='text'>
With nVHE code now fully separated from the rest of the kernel, the effects of
the __hyp_text macro (which had to be applied on all nVHE code) can be
achieved with build rules instead. The macro used to:
  (a) move code to .hyp.text ELF section, now done by renaming .text using
      `objcopy`, and
  (b) `notrace` and `__noscs` would negate effects of CC_FLAGS_FTRACE and
      CC_FLAGS_SCS, respectivelly, now those flags are  erased from
      KBUILD_CFLAGS (same way as in EFI stub).

Note that by removing __hyp_text from code shared with VHE, all VHE code is now
compiled into .text and without `notrace` and `__noscs`.

Use of '.pushsection .hyp.text' removed from assembly files as this is now also
covered by the build rules.

For MAINTAINERS: if needed to re-run, uses of macro were removed with the
following command. Formatting was fixed up manually.

  find arch/arm64/kvm/hyp -type f -name '*.c' -o -name '*.h' \
       -exec sed -i 's/ __hyp_text//g' {} +

Signed-off-by: David Brazdil &lt;dbrazdil@google.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20200625131420.71444-15-dbrazdil@google.com
</content>
</entry>
<entry>
<title>KVM: arm64: Split hyp/debug-sr.c to VHE/nVHE</title>
<updated>2020-07-05T17:38:25Z</updated>
<author>
<name>David Brazdil</name>
<email>dbrazdil@google.com</email>
</author>
<published>2020-06-25T13:14:15Z</published>
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<id>urn:sha1:d400c5b2025c9aeca76213d6bd4138ec39da5cef</id>
<content type='text'>
debug-sr.c contains KVM's code for context-switching debug registers, with some
code shared between VHE/nVHE. These common routines are moved to a header file,
VHE-specific code is moved to vhe/debug-sr.c and nVHE-specific code to
nvhe/debug-sr.c.

Functions are slightly refactored to move code hidden behind `has_vhe()` checks
to the corresponding .c files.

Signed-off-by: David Brazdil &lt;dbrazdil@google.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20200625131420.71444-11-dbrazdil@google.com
</content>
</entry>
</feed>
