Hosts the 0x221E linux distro kernel. https://universe.0xinfinity.dev/distro/kernel/atom?h=master 2026-03-06T12:15:02Z 2026-03-06T12:15:02Z Fabrizio Castro fabrizio.castro.jz@renesas.com 2026-02-03T12:42:46Z urn:sha1:a3f34651de4287138c0da19ba321ad72622b4af3 The HW user manual for the Renesas RZ/V2H(P) SoC (a.k.a r9a09g057) states that only WDT1 is supposed to be accessed by the CA55 cores. WDT0 is supposed to be used by the CM33 core, WDT2 is supposed to be used by the CR8 core 0, and WDT3 is supposed to be used by the CR8 core 1. Remove wdt{0,2,3} from the SoC specific device tree to make it compliant with the specification from the HW manual. This change is harmless as there are currently no users of the wdt{0,2,3} device tree nodes, only the wdt1 node is actually used. Fixes: 095105496e7d ("arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes") Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260203124247.7320-3-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2026-01-09T11:12:39Z Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com 2025-12-24T17:52:04Z urn:sha1:688fded2fc74b0539cd848b775418200c52a1fc2 Add CANFD node to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251224175204.3400062-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2026-01-09T10:47:52Z Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com 2025-12-22T16:42:38Z urn:sha1:03301175a6febb2faf7984e7a2396c345d8774a0 Add RSCI nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251222164238.156985-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2026-01-05T13:37:17Z Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com 2025-11-19T11:05:02Z urn:sha1:92279daefc1740961404bca0a7f5149bf6b23dea Add USB3 PHY/Host nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251119110505.100253-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2026-01-05T13:33:04Z Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com 2025-10-23T21:23:13Z urn:sha1:ebb6adecb992d5c6f16a830b9361092a1e791755 Add DU and DSI nodes to RZ/V2H(P) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251023212314.679303-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2026-01-05T13:33:04Z Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com 2025-10-23T21:23:12Z urn:sha1:0154078db6abbc8f1adc216e1b20472f0b50aaf8 Add FCPV and VSPD nodes to RZ/V2H(P) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251023212314.679303-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2025-11-13T20:19:22Z Ovidiu Panait ovidiu.panait.rb@renesas.com 2025-11-07T21:07:05Z urn:sha1:cfc733da4e79018f88d8ac5f3a5306abbba8ef89 Add RTC node to Renesas RZ/V2H ("R9A09G057") SoC DTSI. Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251107210706.45044-4-ovidiu.panait.rb@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2025-11-13T20:19:22Z Ovidiu Panait ovidiu.panait.rb@renesas.com 2025-10-20T14:31:07Z urn:sha1:1f77aced8c5c6f69566e69f63c3a6c1960f7fc87 The Renesas RZ/V2H SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The device provides real-time temperature measurements for thermal management, utilizing two dedicated channels for temperature sensing: - TSU0, which is located near the DRP-AI block - TSU1, which is located near the CPU and DRP-AI block Since TSU1 is physically closer the CPU and the highest temperature spot, it is used for CPU throttling through a passive trip and cooling map. TSU0 is configured only with a critical trip. Add TSU nodes along with thermal zones and keep them enabled in the SoC DTSI. Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251020143107.13974-4-ovidiu.panait.rb@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2025-10-28T08:23:46Z Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com 2025-10-07T12:15:05Z urn:sha1:32bd03f2555728b7e3304ae1e673ec689580a1e5 Enable the performance monitor unit for the Cortex-A55 cores on the RZ/V2H(P) (R9A09G057) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251007121508.1595889-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2025-10-28T08:23:45Z Kuninori Morimoto kuninori.morimoto.gx@renesas.com 2025-09-24T04:32:24Z urn:sha1:098da100b309be7f3698139ee60c7cfea6a13950 Move the "interrupt-parent = <&gic>" property from the soc node to the root node, and simplify "interrupts-extended = <&gic ...>" to "interrupts = <...>". Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/87ecrw8o87.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>