<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/arch/arm64/boot/dts/microchip, branch linux-6.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2022-06-16T20:45:26Z</updated>
<entry>
<title>arm64: dts: microchip: adjust whitespace around '='</title>
<updated>2022-06-16T20:45:26Z</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzysztof.kozlowski@linaro.org</email>
</author>
<published>2022-05-26T20:41:08Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=09f4933a4fd9ebe333726dd139bd330843d40f28'/>
<id>urn:sha1:09f4933a4fd9ebe333726dd139bd330843d40f28</id>
<content type='text'>
Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment.  No functional
changes (same DTB).

Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/r/20220526204110.831805-1-krzysztof.kozlowski@linaro.org
</content>
</entry>
<entry>
<title>arm64: dts: microchip: align SPI NOR node name with dtschema</title>
<updated>2022-04-26T10:38:17Z</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzysztof.kozlowski@linaro.org</email>
</author>
<published>2022-04-07T14:32:23Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=402eb8ec54b36f8fc0649768c01abb57062d6f8b'/>
<id>urn:sha1:402eb8ec54b36f8fc0649768c01abb57062d6f8b</id>
<content type='text'>
The node names should be generic and SPI NOR dtschema expects "flash".

Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Reviewed-by: Tudor Ambarus &lt;tudor.ambarus@microchip.com&gt;
Link: https://lore.kernel.org/r/20220407143223.295344-2-krzysztof.kozlowski@linaro.org
</content>
</entry>
<entry>
<title>dts: sparx5: Enable ptp interrupt</title>
<updated>2022-03-04T13:03:09Z</updated>
<author>
<name>Horatiu Vultur</name>
<email>horatiu.vultur@microchip.com</email>
</author>
<published>2022-03-04T11:08:54Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=6015fb905d89063231ed33bc15be19ef0fc339b8'/>
<id>urn:sha1:6015fb905d89063231ed33bc15be19ef0fc339b8</id>
<content type='text'>
Add support for ptp interrupt. This interrupt is used when using 2-step
timestamping. For each timestamp that is added in a queue, an interrupt
is generated.

Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>arm64: dts: sparx5: Add the Sparx5 switch frame DMA support</title>
<updated>2021-08-20T13:28:55Z</updated>
<author>
<name>Steen Hegelund</name>
<email>steen.hegelund@microchip.com</email>
</author>
<published>2021-08-19T07:39:40Z</published>
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<id>urn:sha1:920c293af8d01942caa10300ad97eabf778e8598</id>
<content type='text'>
This adds the interrupt for the Sparx5 Frame DMA.

If this configuration is present the Sparx5 SwitchDev driver will use the
Frame DMA feature, and if not it will use register based injection and
extraction for sending and receiving frames to the CPU.

Signed-off-by: Steen Hegelund &lt;steen.hegelund@microchip.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>arm64: dts: sparx5: Add the Sparx5 switch node</title>
<updated>2021-06-24T18:28:13Z</updated>
<author>
<name>Steen Hegelund</name>
<email>steen.hegelund@microchip.com</email>
</author>
<published>2021-06-24T07:07:58Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=d0f482bb06f9447d44d2cae0386a0bd768c3cc16'/>
<id>urn:sha1:d0f482bb06f9447d44d2cae0386a0bd768c3cc16</id>
<content type='text'>
This provides the configuration for the currently available evaluation
boards PCB134 and PCB135.

The series depends on the following series currently on its way
into the kernel:

- Sparx5 Reset Driver
  Link: https://lore.kernel.org/r/20210416084054.2922327-1-steen.hegelund@microchip.com/

Signed-off-by: Steen Hegelund &lt;steen.hegelund@microchip.com&gt;
Signed-off-by: Lars Povlsen &lt;lars.povlsen@microchip.com&gt;
Signed-off-by: Bjarni Jonasson &lt;bjarni.jonasson@microchip.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>arm64: dts: sparx5: Add SGPIO devices</title>
<updated>2020-12-10T10:55:31Z</updated>
<author>
<name>Lars Povlsen</name>
<email>lars.povlsen@microchip.com</email>
</author>
<published>2020-11-13T14:51:51Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=7e1f91cbfa0d330fad61c621389373cff81898fd'/>
<id>urn:sha1:7e1f91cbfa0d330fad61c621389373cff81898fd</id>
<content type='text'>
This adds SGPIO devices for the Sparx5 SoC and configures it for the
applicable reference boards.

Signed-off-by: Lars Povlsen &lt;lars.povlsen@microchip.com&gt;
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Link: https://lore.kernel.org/r/20201113145151.68900-4-lars.povlsen@microchip.com
</content>
</entry>
<entry>
<title>arm64: dts: sparx5: Add reset support</title>
<updated>2020-12-10T10:50:43Z</updated>
<author>
<name>Lars Povlsen</name>
<email>lars.povlsen@microchip.com</email>
</author>
<published>2020-10-06T20:03:16Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=5ef399aa5c5f9c4c2ac9208d1f00e935f13012ce'/>
<id>urn:sha1:5ef399aa5c5f9c4c2ac9208d1f00e935f13012ce</id>
<content type='text'>
This adds reset support to the Sparx5 SoC DT.

Signed-off-by: Lars Povlsen &lt;lars.povlsen@microchip.com&gt;
Link: https://lore.kernel.org/r/20201006200316.2261245-4-lars.povlsen@microchip.com
</content>
</entry>
<entry>
<title>arm64: dts: sparx5: Add spi-nand devices</title>
<updated>2020-09-16T09:39:51Z</updated>
<author>
<name>Lars Povlsen</name>
<email>lars.povlsen@microchip.com</email>
</author>
<published>2020-08-24T20:30:10Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=5df50128050d01d300f28d9bca4dd89d6d24de3d'/>
<id>urn:sha1:5df50128050d01d300f28d9bca4dd89d6d24de3d</id>
<content type='text'>
This patch add spi-nand DT nodes to the applicable Sparx5 boards.

Signed-off-by: Lars Povlsen &lt;lars.povlsen@microchip.com&gt;
Link: https://lore.kernel.org/r/20200824203010.2033-7-lars.povlsen@microchip.com
</content>
</entry>
<entry>
<title>arm64: dts: sparx5: Add spi-nor support</title>
<updated>2020-09-16T09:38:20Z</updated>
<author>
<name>Lars Povlsen</name>
<email>lars.povlsen@microchip.com</email>
</author>
<published>2020-08-24T20:30:09Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=ba4d1c074fd7e5f5d1a5b025b510fd542fc04da5'/>
<id>urn:sha1:ba4d1c074fd7e5f5d1a5b025b510fd542fc04da5</id>
<content type='text'>
This add spi-nor device nodes to the Sparx5 reference boards.

Signed-off-by: Lars Povlsen &lt;lars.povlsen@microchip.com&gt;
Link: https://lore.kernel.org/r/20200824203010.2033-6-lars.povlsen@microchip.com
</content>
</entry>
<entry>
<title>arm64: dts: sparx5: Add SPI controller and associated mmio-mux</title>
<updated>2020-09-16T08:34:21Z</updated>
<author>
<name>Lars Povlsen</name>
<email>lars.povlsen@microchip.com</email>
</author>
<published>2020-08-24T20:30:07Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=08ee16e95492f41d69df3b7fbd942d35dfece6a9'/>
<id>urn:sha1:08ee16e95492f41d69df3b7fbd942d35dfece6a9</id>
<content type='text'>
This adds a SPI controller to the Microchip Sparx5 SoC, as well as the
mmio-mux that is required to select the right SPI interface for a
given SPI device.

Signed-off-by: Lars Povlsen &lt;lars.povlsen@microchip.com&gt;
Link: https://lore.kernel.org/r/20200824203010.2033-4-lars.povlsen@microchip.com
</content>
</entry>
</feed>
