kernel/arch/arm/mm/cache-tauros2.c, branch linux-6.2.y

treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_56.RULE (part 1)

2022-06-10T12:51:35Z

Based on the normalized pattern: this file is licensed under the terms of the gnu general public license version 2 this program is licensed as is without any warranty of any kind whether express or implied extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference. Reviewed-by: Allison Randal Signed-off-by: Thomas Gleixner Signed-off-by: Greg Kroah-Hartman

ARM: l2c: tauros2: use descriptive definitions for register bits

2015-11-26T22:12:26Z

Use descriptive definitions for the Tauros2 register bits, and while we're here, clean up the "Tauros2: %s line fill burt8." message. Signed-off-by: Russell King

ARM: l2c: tauros2: fix OF-enabled non-DT boot

2015-11-26T22:12:02Z

Signed-off-by: Russell King

ARM: convert printk(KERN_* to pr_*

2014-11-21T15:24:50Z

Convert many (but not all) printk(KERN_* to pr_* to simplify the code. We take the opportunity to join some printk lines together so we don't split the message across several lines, and we also add a few levels to some messages which were previously missing them. Tested-by: Andrew Lunn Tested-by: Felipe Balbi Signed-off-by: Russell King

ARM: cache-tauros2: remove ARMv6 code

2014-03-27T01:49:24Z

When building a kernel with support for both ARMv6 and ARMv7 but no MMU, the call from tauros2_internal_init to adjust_cr causes a link error. While that could probably be resolved, we don't actually support cache-tauros2 on ARMv6 any more. All PJ4 CPU implementations support both ARMv6 and ARMv7 and we already assume that we are using them only in ARMv7 mode. Removing the ARMv6 code path reduces the code size and avoids the linker error. Signed-off-by: Arnd Bergmann Acked-by: Haojian Zhuang

ARM: cache: add dt support for tauros2 cache

2012-08-16T08:16:50Z

Signed-off-by: Chao Xie Signed-off-by: Haojian Zhuang

ARM: cache: add extra feature enable for tauros2

2012-08-16T08:16:27Z

The extra feature may be used by SOCs are prefetch, burst8, write buffer coalesce Signed-off-by: Chao Xie Signed-off-by: Haojian Zhuang

ARM: cache: add cputype.h for tauros2

2012-08-16T08:16:17Z

Signed-off-by: Chao Xie Signed-off-by: Haojian Zhuang

ARM: cache: fix uninitialized ptr in tauros2_init

2012-08-16T08:16:06Z

init the variable "mode" to NULL to ensure the later NULL checking is taking effect. Signed-off-by: Chao Xie Signed-off-by: Haojian Zhuang

ARM: cache: tauros2: add disable and resume callback

2012-05-07T03:43:48Z

For the SOC chips using tauros2 cache, will need disable and resume tauros2 cache for SOC suspend/resume. Signed-off-by: Chao Xie Signed-off-by: Haojian Zhuang