kernel/arch/arm/mach-omap2/omap-hotplug.c, branch linux-6.2.y

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

2019-06-19T15:09:55Z

Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Enrico Weigelt Reviewed-by: Kate Stewart Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman

ARM: omap2+: Revert omap-smp.c changes resetting CPU1 during boot

2017-03-27T17:10:42Z

Commit 3251885285e1 ("ARM: OMAP4+: Reset CPU1 properly for kexec") started unconditionally resetting CPU1 because of a kexec boot issue I was seeing earlier on omap4 when doing kexec boot between two different kernel versions. This caused issues on some systems. We should only reset CPU1 as a last resort option, and try to avoid it where possible. Doing an unconditional CPU1 reset causes issues for example when booting a bootloader configured secure OS running on CPU1 as reported by Andrew F. Davis . We can't completely remove the reset of CPU1 as it would break kexec booting from older kernels. But we can limit the CPU1 reset to cases where CPU1 is wrongly parked within the memory area used by the booting kernel. Then later on we can add support for parking CPU1 for kexec out of the SDRAM back to bootrom. So let's first fix the regression reported by Andrew by making CPU1 reset conditional. To do this, we need to: 1. Save configured AUX_CORE_BOOT_1 for later 2. Modify AUX_CORE_BOOT_0 reading code to for HS SoCs to return the whole register instead of the CPU mask 3. Check if CPU1 is wrongly parked into the booting kernel by the previous kernel and reset if needed Fixes: 3251885285e1 ("ARM: OMAP4+: Reset CPU1 properly for kexec") Reported-by: Andrew F. Davis Cc: Andrew F. Davis Cc: Keerthy Cc: Russell King Cc: Santosh Shilimkar Cc: Tero Kristo Tested-by: Keerthy Tested-by: Andrew F. Davis Signed-off-by: Tony Lindgren

ARM: OMAP4+: Allow kexec on SMP variants

2016-06-23T05:57:02Z

Kexec needs omap4_cpu_kill, otherwise kexec will produce on SMP: kexec_load failed: Invalid argument Acked-by: Santosh Shilimkar Tested-by: Keerthy Signed-off-by: Tony Lindgren

ARM: Remove __ref on hotplug cpu die path

2015-10-22T16:55:03Z

Now that __cpuinit has been removed, the __ref markings on these functions are useless. Remove them. This also reduces the size of the multi_v7_defconfig image: $ size before after text data bss dec hex filename 12683578 1470996 348904 14503478 dd4e36 before 12683274 1470996 348904 14503174 dd4d06 after presumably because now we don't have to jump to code in the .ref.text section and/or the noinline marking is removed. Cc: Shiraz Hashim Cc: Stephen Warren Cc: Alexandre Courbot Cc: Lorenzo Pieralisi Cc: Will Deacon Cc: Cc: Cc: Cc: Acked-by: Tony Lindgren Acked-by: Barry Song Acked-by: Andy Gross Acked-by: Viresh Kumar Acked-by: Thierry Reding Acked-by: Linus Walleij Acked-by: Sudeep Holla Acked-by: Mark Rutland Signed-off-by: Stephen Boyd Signed-off-by: Olof Johansson

ARM: OMAP2+: raw read and write endian fix

2014-05-08T14:09:53Z

All OMAP IP blocks expect LE data, but CPU may operate in BE mode. Need to use endian neutral functions to read/write h/w registers. I.e instead of __raw_read[lw] and __raw_write[lw] functions code need to use read[lw]_relaxed and write[lw]_relaxed functions. If the first simply reads/writes register, the second will byteswap it if host operates in BE mode. Changes are trivial sed like replacement of __raw_xxx functions with xxx_relaxed variant. Signed-off-by: Victor Kamensky Signed-off-by: Taras Kondratiuk Signed-off-by: Tony Lindgren

ARM: OMAP4+: Remove the un-necessary cache flush from hotplug code

2013-03-28T07:25:59Z

This was added with intial port where OMAP PM support wasn't existing and only simple WFI based hooks were used. This should have been cleaned up while adding the PM support but some how fall through cracks. So remove the cache flush code which is no longer needed now. Signed-off-by: Santosh Shilimkar

Merge branch 'multiplatform/smp_ops' into next/multiplatform

2012-09-22T07:16:04Z

* multiplatform/smp_ops: ARM: consolidate pen_release instead of having per platform definitions ARM: smp: Make SMP operations mandatory ARM: SoC: convert spear13xx to SMP operations ARM: SoC: convert imx6q to SMP operations ARM: SoC: convert highbank to SMP operations ARM: SoC: convert shmobile SMP to SMP operations ARM: SoC: convert ux500 to SMP operations ARM: SoC: convert MSM to SMP operations ARM: SoC: convert Exynos4 to SMP operations ARM: SoC: convert Tegra to SMP operations ARM: SoC: convert OMAP4 to SMP operations ARM: SoC: convert VExpress/RealView to SMP operations ARM: SoC: add per-platform SMP operations Conflicts due to file moves or removals in: arch/arm/mach-msm/board-msm8960.c arch/arm/mach-msm/board-msm8x60.c arch/arm/mach-tegra/board-harmony.c arch/arm/mach-tegra/board-trimslice.c Conflicts due to board file cleanup: arch/arm/mach-tegra/board-paz00.c Conflicts due to cpu hotplug addition: arch/arm/mach-tegra/hotplug.c Signed-off-by: Olof Johansson

ARM: OMAP2+: Make omap-wakeupgen.h local

2012-09-20T22:02:37Z

This can be local to mach-omap2. Signed-off-by: Tony Lindgren

ARM: SoC: convert OMAP4 to SMP operations

2012-09-13T13:34:57Z

Convert OMAP4 to use struct smp_operations to provide its SMP and CPU hotplug operations. Tested on both Panda and IGEPv2 (MULTI_OMAP kernel) Signed-off-by: Marc Zyngier Reviewed-by: Santosh Shilimkar Acked-by: Nicolas Pitre Signed-off-by: Arnd Bergmann

ARM: OMAP5: Add the WakeupGen IP updates

2012-07-09T13:44:39Z

OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5. - Additional 32 interrupt support is added w.r.t OMAP4 design. - The AUX CORE boot registers are now made accessible from non-secure SW. - SAR offset are changed and PTMSYNC* registers are removed from SAR. Patch updates the WakeupGen code accordingly. Signed-off-by: R Sricharan Signed-off-by: Santosh Shilimkar