kernel/arch/arm/include/asm/hardware/cache-tauros2.h, branch linux-6.2.yHosts the 0x221E linux distro kernel.https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y2022-06-10T12:51:35Ztreewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_56.RULE (part 1)2022-06-10T12:51:35ZThomas Gleixnertglx@linutronix.de2022-06-07T14:11:14Zurn:sha1:0fdebc5ec2ca492d69df2d93a6a7abade4941aae
Based on the normalized pattern:
this file is licensed under the terms of the gnu general public
license version 2 this program is licensed as is without any warranty
of any kind whether express or implied
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference.
Reviewed-by: Allison Randal <allison@lohutok.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
ARM: cache: add extra feature enable for tauros22012-08-16T08:16:27ZChao Xiexiechao.mail@gmail.com2012-07-31T06:13:12Zurn:sha1:38f2e3772429f29a273a2ed7e95dd7a41f662f06
The extra feature may be used by SOCs are prefetch, burst8,
write buffer coalesce
Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
ARM: Add Tauros2 L2 cache controller support2009-11-27T20:43:21ZLennert Buytenhekbuytenh@marvell.com2009-11-24T17:33:52Zurn:sha1:573a652fb0da50a1ff3fca2c67afd81138fd06d2
Support for the Tauros2 L2 cache controller as used with the PJ1
and PJ4 CPUs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>